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AD8571 View Datasheet(PDF) - Unspecified

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AD8571 Datasheet PDF : 19 Pages
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AD8571/AD8572/AD8574
Input Overvoltage Protection
Although the AD857x is a rail-to-rail input amplifier, care should
be taken to ensure that the potential difference between the inputs
does not exceed 5 V. Under normal operating conditions, the
amplifier will correct its output to ensure the two inputs are at
the same voltage. However, if the device is configured as a com-
parator, or is under some unusual operating condition, the input
voltages may be forced to different potentials. This could cause
excessive current to flow through internal diodes in the AD857x
used to protect the input stage against overvoltage.
If either input exceeds either supply rail by more than 0.3 V, large
amounts of current will begin to flow through the ESD protection
diodes in the amplifier. These diodes are connected between the
inputs and each supply rail to protect the input transistors against
an electrostatic discharge event and are normally reverse-biased.
However, if the input voltage exceeds the supply voltage, these
ESD diodes will become forward-biased. Without current-limiting,
excessive amounts of current could flow through these diodes
causing permanent damage to the device. If inputs are subject to
overvoltage, appropriate series resistors should be inserted to limit
the diode current to less than 2 mA maximum.
Output Phase Reversal
Output phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. As common-mode
voltage is moved outside of the common-mode range, the outputs
of these amplifiers will suddenly jump in the opposite direction to
the supply rail. This is the result of the differential input pair shut-
ting down, causing a radical shifting of internal voltages which
results in the erratic output behavior.
The AD857x amplifier has been carefully designed to prevent
any output phase reversal, provided both inputs are maintained
within the supply voltages. If one or both inputs could exceed
either supply voltage, a resistor should be placed in series with
the input to limit the current to less than 2 mA. This will ensure
the output will not reverse its phase.
Capacitive Load Drive
The AD857x has excellent capacitive load-driving capabilities
and can safely drive up to 10 nF from a single 5 V supply.
Although the device is stable, capacitive loading will limit the
bandwidth of the amplifier. Capacitive loads will also increase
the amount of overshoot and ringing at the output. An R-C
snubber network, Figure 52, can be used to compensate the
amplifier against capacitive load ringing and overshoot.
Although the snubber will not recover the loss of amplifier band-
width from the load capacitance, it will allow the amplifier to drive
larger values of capacitance while maintaining a minimum of over-
shoot and ringing. Figure 53 shows the output of an AD857x
driving a 1 nF capacitor with and without a snubber network.
WITH
SNUBBER
10s
WITHOUT
SNUBBER
VS = 5V
CLOAD = 4.7nF
100mV
Figure 53. Overshoot and Ringing are Substantially
Reduced Using a Snubber Network
The optimum value for the resistor and capacitor is a function of
the load capacitance and is best determined empirically since actual
CLOAD will include stray capacitances and may differ substantially
from the nominal capacitive load. Table I shows some snubber
network values that can be used as starting points.
Table I. Snubber Network Values for Driving Capacitive Loads
CLOAD
1 nF
4.7 nF
10 nF
RX
200
60
20
CX
1 nF
0.47 µF
10 µF
Power-Up Behavior
On power-up, the AD857x will settle to a valid output within 5 µs.
Figure 54a shows an oscilloscope photo of the output of the ampli-
fier along with the power supply voltage, and Figure 54b shows the
test circuit. With the amplifier configured for unity gain, the device
takes approximately 5 µs to settle to its final output voltage. This
turn-on response time is much faster than most other autocorrection
amplifiers, which can take hundreds of microseconds or longer for
their output to settle.
VIN
200mV p-p
5V
AD857x
RX
60
CX
0.47F
VOUT
CL
4.7nF
Figure 52. Snubber Network Configuration for Driving
Capacitive Loads
VOUT
0V
V+
0V
5s
1V
BOTTOM TRACE = 2V/DIV
TOP TRACE = 1V/DIV
Figure 54a. AD857x Output Behavior on Power-Up
–14–
REV. 0
 

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