Electronic component search and free download site.
Transistors,MosFET ,Diode,Integrated circuits

AD7927 View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
AD7927 8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP ETC
Unspecified 
AD7927 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
AD7927
SERIAL INTERFACE
Figure 17 shows the detailed timing diagram for serial interfacing
to the AD7927. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7927 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and will
require 16 SCLK cycles to complete. The track and hold will
go back into track on the 14th SCLK falling edge as shown in
Figure 17 at point B, except when the write is to the Shadow
Register, in which case the track and hold will not return to
track until the rising edge of CS, i.e., point C in Figure 18. On
the 16th SCLK falling edge the DOUT line will go back into
three-state. If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated and the DOUT line
will go back into three-state and the Control Register will not be
updated; otherwise DOUT returns to three-state on the 16th
SCLK falling edge, as shown in Figure 17. Sixteen serial clock
cycles are required to perform the conversion process and to
access data from the AD7927. For the AD7927, the 12 bits of
data are preceded by a leading zero and the three channel address
bits ADD2 to ADD0, identifying which channel the result corre-
sponds to. CS going low provides the leading zero to be read in by
the microcontroller or DSP. The three remaining address bits and
data bits are then clocked out by subsequent SCLK falling edges
beginning with the first address bit ADD2, thus the first falling
clock edge on the serial clock has a leading zero provided and
also clocks out address bit ADD2. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.
Writing of information to the Control Register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the MSB,
i.e., the WRITE bit, has been set to 1. If the Control Register is
programmed to use the Shadow Register, then the writing of
information to the Shadow Register will take place on all 16 SCLK
falling edges in the next serial transfer as shown for example on the
AD7927 in Figure 18. Two sequence options can be programmed
in the Shadow Register. If the user does not want to program a
second sequence, then the eight LSBs should be filled with zeros.
The Shadow Register will be updated upon the rising edge of
CS and the track and hold will begin to track the first channel
selected in the sequence.
The 16-bit word read from the AD7927 will always contain a
leading zero, three channel address bits that the conversion
result corresponds to, followed by the 12-bit conversion result.
Writing Between Conversions
As outlined in the Operating Modes section, not less than 5 ms
should be left between consecutive valid conversions. However,
there is one case where this does not necessarily mean that at least
5 ms should always be left between CS falling edges. Consider the
case when writing to the AD7927 to power it up from shutdown
prior to a valid conversion. The user must write to the part to tell
it to power up before it can convert successfully. Once the serial
write to power up has finished, one may wish to perform the con-
version as soon as possible and not have to wait a further 5 ms
before bringing CS low for the conversion. In this case, as long
as there is a minimum of 5 ms between each valid conversion, then
only the quiet time between the CS rising edge at the end of the
write to power up and the next CS falling edge for a valid con-
version needs to be met. Figure 19 illustrates this point. Note
CS
SCLK
tCONVERT
t2
t6
1
2
3
4
5
t3
t7
t4
DOUT
ADD2
ADD1
ADD0
THREE-
STATE
3 IDENTIFICATION BITS
ZERO t9
DB11
DB10
t10
DIN
WRITE SEQ
DONTC ADD2
ADD1
ADD0
B
13
14
t5
DB2
DB1
tQUIET
15
16
t8
DB0
t11
THREE-
STATE
DONTC DONTC
DONTC
Figure 17. Serial Interface Timing Diagram
CS
SCLK
t2
1
tCONVERT
t6
2
3
4
5
DOUT
DIN
t3
ADD2
ADD1
ADD0
THREE-
STATE
3 IDENTIFICATION BITS
ZERO t9
VIN0
VIN1
VIN2
VIN3
SEQUENCE 1
t4
DB11
t7
DB10
t10
VIN4
VIN5
C
13
14
t5
DB2
DB1
15
t8
DB0
16
t11
THREE-
STATE
VIN5
SEQUENCE 2
VIN6
VIN7
Figure 18. Writing to Shadow Register Timing Diagram
REV. 0
–17–
Direct download click here

 

Share Link : 
All Rights Reserved© datasheetq.com 2015 - 2019  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]