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AD7927 View Datasheet(PDF) - Unspecified

Part NameDescriptionManufacturer
AD7927 8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP ETC
AD7927 Datasheet PDF : 20 Pages
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Analog Input Selection
Any one of eight analog input channels may be selected for
conversion by programming the multiplexer with the address bits
ADD2 though ADD0 in the Control Register. The channel con-
figurations are shown in Table II.
The AD7927 may also be configured to automatically cycle through
a number of channels as selected. The sequencer feature is
accessed via the SEQ and SHADOW bits in the Control Register
(see Table IV). The AD7927 can be programmed to continuously
convert on a selection of channels in ascending order. The analog
input channels to be converted on are selected through program-
ming the relevant bits in the Shadow Register (see Table V).
The next serial transfer will then act on the sequence programmed
by executing a conversion on the lowest channel in the selection.
The next serial transfer will result in the conversion on the next
highest channel in the sequence, and so on.
It is not necessary to write to the Control Register once a sequencer
operation has been initiated. The WRITE bit must be set to
zero or the DIN line tied low to ensure that the Control Register
is not accidently overwritten, or the sequence operation inter-
rupted. If the Control Register is written to at any time during
the sequence, the user must ensure that the SEQ and SHADOW
bits are set to 1,0 to avoid interrupting the automatic conversion
sequence. This pattern will continue until such time as the AD7927
is written to and the SEQ and SHADOW bits are configured with
any bit combination except 1,0. On completion of the sequence,
the AD7927 sequencer will return to the first selected channel
in the Shadow Register and commence the sequence again.
Rather than selecting a particular sequence of channels, a number
of consecutive channels beginning with Channel 0 may also be
programmed via the Control Register alone without needing to
write to the Shadow Register. This is possible if the SEQ and
SHADOW bits are set to 1,1. The channel address bits ADD2
through ADD0 will then determine the final channel in the con-
secutive sequence. The next conversion will be on Channel 0,
then Channel 1, and so on until the channel selected via the ad-
dress bits ADD2 through ADD0 is reached. The cycle will begin
again on the next serial transfer provided the WRITE bit is set
to low, or if high, that the SEQ and SHADOW bits are set to
1,0; then the ADC will continue its preprogrammed automatic
sequence uninterrupted.
Regardless of which channel selection method is used, the 16-bit
word output from the AD7927 during each conversion will
always contain one leading zero, three channel address bits
that the conversion result corresponds to, followed by the 12-bit
conversion result. (See the Serial Interface section.)
Digital Inputs
The digital inputs applied to the AD7927 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digital
inputs applied can go to 7 V and are not restricted by the AVDD
+ 0.3 V limit as on the analog inputs.
Another advantage of SCLK, DIN, and CS not being restricted
by the AVDD + 0.3 V limit is that possible power supply sequencing
issues are avoided. If CS, DIN, or SCLK are applied before
AVDD, there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V was applied prior to AVDD.
The AD7927 also has the VDRIVE feature. VDRIVE controls the voltage
at which the serial interface operates. VDRIVE allows the ADC
to easily interface to both 3 V and 5 V processors. For example,
if the AD7927 were operated with an AVDD of 5 V, the VDRIVE
pin could be powered from a 3 V supply. The AD7927 has a
larger dynamic range with an AVDD of 5 V while still being
able to interface to 3 V processors. Care should be taken to
ensure VDRIVE does not exceed AVDD by more than 0.3 V. (See
Absolute Maximum Ratings.)
The Reference
An external reference source should be used to supply the 2.5 V
reference to the AD7927. Errors in the reference source will result
in gain errors in the AD7927 transfer function and will add to the
specified full-scale errors of the part. A capacitor of at least 0.1 mF
should be placed on the REFIN pin. Suitable reference sources for
the AD7927 include the AD780, REF 193, and the AD1582.
If 2.5 V is applied to the REFIN pin, the analog input range can
be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the RANGE bit in the Control Register.
The AD7927 has a number of different modes of operation,
which are designed to provide flexible power management options.
These options can be chosen to optimize the power dissipation/
throughput rate ratio for differing application requirements. The
mode of operation of the AD7927 is controlled by the power
management bits, PM1 and PM0, in the Control Register, as
detailed in Table III. When power supplies are first applied to
the AD7927, care should be taken to ensure that the part is
placed in the required mode of operation. (See the Powering
Up the AD7927 section.)
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate perfor-
mance as the user does not have to worry about any power-up
times with the AD7927 remaining fully powered at all times.
Figure 12 shows the general diagram of the operation of the
AD7927 in this mode.
The conversion is initiated on the falling edge of CS and the track
and hold will enter hold mode as described in the Serial Interface
section. The data presented to the AD7927 on the DIN line during
the first 12 clock cycles of the data transfer are loaded into the
Control Register (provided WRITE bit is 1). If data is to be
written to the Shadow Register (SEQ = 0, SHADOW = 1 on
previous write), data presented on the DIN line during the first
16 SCLK cycles is loaded into the Shadow Register. The part
will remain fully powered up in Normal mode at the end of the
conversion as long as PM1 and PM0 are set to 1 in the write
transfer during that conversion. To ensure continued operation
in Normal mode, PM1 and PM0 are both loaded with 1 on every
data transfer. Sixteen serial clock cycles are required to complete
the conversion and access the conversion result. The track and
hold will go back into track on the 14th SCLK falling edge. CS
may then idle high until the next conversion or may idle low until
sometime prior to the next conversion (effectively idling CS low).
For specified performance, the throughput rate should not exceed
200 kSPS, which means there should be no less than 5 ms between
consecutive falling edges of CS when converting. The actual
frequency of SCLK used will determine the duration of the
conversion within this 5 ms cycle; however, once a conversion is
complete and CS has returned high, a minimum of the quiet
time, tquiet, must elapse before bringing CS low again to initiate
another conversion.
REV. 0
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