The ISL6225 is a dual channel PWM controller intended for
use in power supplies for graphic chipset, SDRAM, DDR
DRAM or other low voltage power applications in modern
notebook and sub-notebook PCs. The IC integrates two
control circuits for two synchronous buck converters. The
output voltage of each controller can be set in the range of
0.9V to 5.5V by an external resistive divider. Out-of-phase
operation with 180 degree phase shift reduces input current
The synchronous buck converters can operate from either
an unregulated DC source such as a notebook battery with a
voltage ranging from 5.0V to 24V, or from a regulated system
rail of 3.3V or 5V. In either mode of operation the controller is
biased from the +5V source.
The controllers operate in the current mode with input
voltage feed-forward for simplified feedback loop
compensation and reduced effect of the input voltage
variation. An integrated feedback loop compensation
dramatically reduces the number of external components.
Depending on the load level, converters can operate either
in a fixed-frequency mode or in a hysteretic mode. Switch-
over to the hysteretic mode operation at light loads improves
the converters' efficiency and prolongs battery run time. The
hysteretic mode of operation can be inhibited independently
for each channel if a variable frequency operation is not
The ISL6225 has a special means to rearrange its internal
architecture into a complete DDR solution. When DDR input
is set high, the second channel can provide the capability to
track the output voltage of the first channel. The buffered
reference voltage required by DDR memory chips is also
The Power-On Reset (POR) function continually monitors
the bias supply voltage on the VCC pin and initiates soft-start
operation after the input supply voltage exceeds 4.5V.
Should this voltage drop lower than 4.0V, the POR disables
When soft-start is initiated, the voltage on the SOFT pin
starts to ramp gradually due to the 5µA current sourced into
the external soft-start capacitor. The output voltage starts to
follow the soft-start voltage.
When the SOFT pin voltage reaches a level of 0.9V, the
output voltage comes into regulation while the soft-start pin
voltage continues to rise. When the SOFT voltage reaches
1.5V, the power good (PGOOD), the mode control, and the
fault functions are enabled, as depicted in Figure 3.
FIGURE 3. START UP
This completes the soft-start sequence. Further rise of pin
voltage does not affect the output voltage. During the soft-
start, the converter always operates in continuous
conduction mode independently of the load level or FCCM
The soft-start time (the time from the moment when EN
becomes high to the moment when PGOOD is reported) is
determined by the following equation.
The time it takes the output voltage to come into regulation
can be obtained from the following equation.
TRISE = 0.6 × TSOFT
Having such a spread between the time when the output
voltage reaches the regulation point and the moment when
PGOOD is reported allows for a fault-safe test mode by
means of an external circuit that clamps the SOFT pin
voltage on the level 0.9V < VSOFT < 1.5V.
Output Voltage Program
The output voltage of either channel is set by a resistive divider
from the output to ground. The center point of the divider is
connected to VSEN pin as shown in Figure 4. The output
voltage value is determined by the following equation.
Where 0.9V is the value of the internal reference. The VSEN
pin voltage is also used by the controller for the power good
function and to detect Undervoltage and Overvoltage
December 28, 2004