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6225CA Просмотр технического описания (PDF) - Unspecified

Номер в каталогеКомпоненты Описаниепроизводитель
6225CA Dual Mobile-Friendly PWM Controller with DDR Memory Option ETC
Unspecified 
6225CA Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Block Diagram
BOOT1
UGATE1
SOFT1
PG1 EN1 VOUT1
VCC GND
VOUT2 EN2 REF/PG2 SOFT2
BOOT2
UGATE2
PHASE1
PGND1
LGATE1
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
DDR=1
DDR=0
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
PWM/HYS TRANSITION
PHASE2
PGND2
LGATE2
VCC
+
MODE CHANGE COMP 1
-
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
HYSTERETIC COMPARATOR 1 - PWM OR HYS MODE
+
VHYS=15mV
1M
15.2pF
VSEN1
500k
300k
1.3pF
-
Σ
+
+ 0.9V REFERENCE
ERROR AMP 1
ISEN1 100
CURRENT
SAMPLE
OCSET1
-
+
CURRENT
SAMPLE
+ 0.9V REFERENCE
OV UV
PGOOD
VOLTS/SEC
CLAMP
-
PWM1
+
POR
ENABLE
BIAS SUPPLIES
REFERENCE
FAULT LATCH
SOFT-START
DDR MODE
CONTROL
OC1 DDR OC2
OV UV
PGOOD
VOLTS/SEC
CLAMP
PWM2
-
+
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
DDR EN1 EN2
VIN
CH1CH2 φ
0 11
0 24.0V
180º
4.2 < VIN < 24.0V
111
VIN to GND
90º
VCC
+
MODE CHANGE COMP 2
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO CHANGE
PWM OR HYS MODE
-
- HYSTERETIC COMPARATOR 2
VHYS=15mV
+
15.2pF
1M
500k
1.3pF
-
Σ
+
ERROR AMP 2
300k
VSEN2
DDR=0 DDR=1
0.9V REFERENCE +
-
CURRENT
+
SAMPLE
0.9V REFERENCE +
100ISEN2
CURRENT
SAMPLE
DDR=0 OCSET2
DDR=1
1/3
OCSET1
1/32
ISEN1
-
OC1
+
VIN
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVER-CURRENT FAULT
DDR
OC2
-
+
VCC
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVER-CURRENT FAULT
1/32
ISEN2
+
-
1/3
OCSET2
DDR VREF
BUFFER AMP
+
-
DDR VTT
REFERENCE
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