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M41T0 View Datasheet(PDF) - Unspecified

Part Name
Description
Manufacturer
M41T0
ETC
Unspecified ETC
M41T0 Datasheet PDF : 22 Pages
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M41T0
Operation
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T0 slave receiver. Bus protocol is
shown in Figure 10 on page 12. Following the START condition and slave address, a logic '0'
(R/W = 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41T0
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte (see
Figure 7).
Figure 7. Slave address location
R/W
START
SLAVE ADDRESS
A
11 0100 0
Figure 8. READ mode sequence
AI00602
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (An)
S
DATA n
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+1
DATA n+X P
AI00899
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