P4C422-10SM View Datasheet(PDF) - Performance Semiconductor
Part Name
Description
Manufacturer
P4C422-10SM Datasheet PDF : 10 Pages
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P4C422
FUNCTIONAL DESCRIPTION
An active LOW write enable (WE) controls the writing/
reading operation of the memory. When the chip select
one (CS 1) and the write enable (WE) are LOW and the chip
select two (CS2) is HIGH, the information on data inputs
(D0 through D3) is written into the addressed memory word
and preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
TRUTH TABLE
Mode
Standby
CS2
CS
1
WE
OE
LXXX
Standby
XHXX
DOUT Disabled H L X H
Read
HLHL
Write
HLLX
Output
High Z
High Z
High Z
DOUT
High Z
recovery times by eliminating the “write recovery glitch.”
Reading is performed with chip selct one (CS 1) LOW, chip
select two (CS2) HIGH, write enable (WE) HIGH and
output enable (OE) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O through O ). The outputs of the memory go to an
0
3
inactive high impedance state whenever chip select one
(CS1) is HIGH, or during the write operation when write
enable (WE) is LOW.
Notes:
H
= HIGH
L
= Low
X
= Don't Care
HIGH Z = Implies outputs are disabled or off. This condition
is defined as high impedance state for the
P4C422.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10% except as noted, All Temperature Ranges)(2)
Sym.
Parameter
-10*
-12
-15
-20
-25
-35
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
tRC
Read Cycle Time (5)
tACS
Chip Select Time (5)
tZRCS
Chip Select to High-Z (6)
tAOS
tZROS
Output Enable Time
Output Enable to High-Z (6)
tAA
Address Access Time (5)
*VCC = 5V ± 5%
12
12
15
20
25
35
ns
7.5
8
8
12
15
25 ns
8
10
12
15
20
30 ns
7.5
8
8
12
15
25 ns
8
10
12
15
20
30 ns
10
12
15
20
25
35 ns
TIMING WAVEFORM OF READ CYCLE
Document # SRAM101 REV. A
Page 3 of 10
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