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OP162GS View Datasheet(PDF) - Analog Devices

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Description
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OP162GS Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
VS = 5V
AV = 1
100
90
CL = 300pF
RL = 10k
WITH SNUBBER:
RX = 140
CX = 10nF
10
0%
50mV
1µs
Figure 42. A Photo of a Nice Square Wave at the Output
The network operates in parallel with the load capacitor, CL,
and provides compensation for the added phase lag. The actual
values of the network resistor and capacitor are empirically
determined to minimize overshoot and maximize unity-gain
bandwidth. Table 6 shows a few sample snubber networks for
large load capacitors.
Table 6. Snubber Networks for Large Capacitive Loads
CLOAD
RX
CX
< 300 pF
140 Ω
10 nF
500 pF
100 Ω
10 nF
1 nF
80 Ω
10 nF
10 nF
10 Ω
47 nF
Higher load capacitance will reduce the unity-gain bandwidth
of the device. Figure 43 shows unity-gain bandwidth vs.
capacitive load. The snubber network does not provide any
increase in bandwidth, but it substantially reduces ringing and
overshoot, as shown between Figure 41 and Figure 42.
10
9
8
7
6
5
4
3
2
1
0
10pF
100pF
1nF
CLOAD
10nF
Figure 43. Unity-Gain Bandwidth vs. CLOAD
TOTAL HARMONIC DISTORTION AND CROSSTALK
The OPx62 device family offers low total harmonic distortion
making it an excellent choice for audio applications. Figure 44
shows a graph of THD plus noise figures at 0.001% for the
OP462.
OP162/OP262/OP462
Figure 45 shows the worst case crosstalk between two amplifiers
in the OP462. A 1 V rms signal is applied to one amplifier while
measuring the output of an adjacent amplifier. Both amplifiers
are configured for unity gain and supplied with ±2.5 V.
0.010
VS = ±2.5V
AV = 1
VIN = 1.0V rms
RL = 10k
BANDWIDTH:
<10Hz TO 22kHz
0.001
0.0001
20
100
1k
FREQUENCY (Hz)
10k 20k
Figure 44. THD + N vs. Frequency
–40
–50
AV = 1
VIN = 1.0V rms
(0dBV)
–60
–70
RL
VS
=
=
±120.k5V
–80
–90
–100
–110
–120
–130
–140
20
100
1k
FREQUENCY (Hz)
10k 20k
Figure 45. Crosstalk vs. Frequency
PCB LAYOUT CONSIDERATIONS
Because the OP162/OP262/OP462 can provide gains at high
frequency, careful attention to board layout and component
selection is recommended. As with any high speed application,
a good ground plane is essential to achieve the optimum
performance. This can significantly reduce the undesirable
effects of ground loops and I × R losses by providing a low
impedance reference point. Best results are obtained with a
multilayer board design with one layer assigned to ground
plane.
Use chip capacitors for supply bypassing, with one end of the
capacitor connected to the ground plane and the other end
connected within 1/8 inch of each power pin. An additional
large tantalum electrolytic capacitor (4.7 µF to 10 µF) should be
connected in parallel. This capacitor provides current for fast,
large-signal changes at the device’s output; therefore, it does not
need to be placed as close to the supply pins.
Rev. F | Page 15 of 20
 

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