SAA7111 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
SAA7111 Datasheet PDF : 64 Pages
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Philips Semiconductors
Video Input Processor (VIP)
Product specification
SAA7111
SYMBOL
RES
CE
VDD4
VSS4
n.c.
n.c.
HS
RTS1
RTS0
VS
HREF
VSS3
VDD3
VPO (15 to 10)
VSS2
VDD2
PINS
PLCC68 QFP64
32
23
33
24
34
25
35
26
36
−
37
−
38
27
39
28
40
29
41
30
42
31
43
44
45 to 50
32
33
34 to 39
51
40
52
41
I/O
O
I
P
GND
−
−
O
O
O
O
O
GND
P
O
GND
P
DESCRIPTION
Reset output (active LOW); sets the device into a defined state.
All data outputs are in high impedance state. The I2C-bus is reset
(waiting for start condition) note 4.
Chip enable; connection to ground forces a reset.
Positive digital supply voltage 4 (+5 V).
Digital ground for positive supply voltage 4.
Not connected.
Not connected.
Horizontal sync output signal (programmable); the positions of the
positive and negative slopes are programmable in 8 LLC increments
over a complete line (equals 64 µs) via I2C-bus bytes HSB and HSS.
Fine position adjustment in 2 LLC increments can be performed via
I2C-bits HDEL1 and HDEL0.
Two functions output; controlled by I2C-bit RTSE1.
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the
inverted and non-inverted R − Y component for PAL signals.
RTSE1 = 1: H-PLL locked indicator; a high state indicates that the
internal horizontal PLL has locked.
Two functions output; controlled by I2C-bit RTSE0.
RTSE0 = 0: odd/even field identification (HIGH = odd field).
RTSE0 = 1: vertical locked indicator; a HIGH state indicates that the
internal VNL has locked.
Vertical sync output signal (enabled via I2C-bit OEHV); this signal
indicates the vertical sync with respect to the YUV output. The HIGH
period of this signal is approximately six lines if the vertical noise
limiter (VNL) function is active. The positive slope contains the phase
information for a deflection controller.
Horizontal reference output signal (enabled via I2C-bit OEHV); this
signal is used to indicate data on the digital YUV bus. The positive
slope marks the beginning of a new active line. The HIGH period of
HREF is 720 Y samples long. HREF can be used to synchronize data
multiplexer/demultiplexers. HREF is also present during the vertical
blanking interval.
Digital ground for positive supply voltage 3.
Positive digital supply voltage 3 (+5 V).
Digital VPO-bus (Video Port Out) output signal; higher bits of the
16-bit YUV-bus or the 16-bit RGB-bus output signal. The output data
rate, the format and multiplexing scheme of the VPO-bus are
controlled via I2C-bits OFTS0 and OFTS1. With I2C-bit VIPB = 1 the
six MSBs of the digitized input signal (AD1 [7 to 2]) are connected to
these outputs.
Digital ground for positive supply voltage 2.
Positive digital supply voltage 2 (+5 V).
1998 May 15
7
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