Philips Semiconductors
Video Input Processor (VIP)
Product specification
SAA7111
16.2.15 SUBADDRESS 10
Table 26 Format/delay control SA 10
LUMINANCE DELAY COMPENSATION
(STEPS IN 2/LLC)
−4...
...0...
...3
YDEL2
1
0
0
CONTROL BITS D2 to D0
YDEL1
0
0
1
YDEL0
0
0
1
Table 27 VREF pulse position and length VRLN SA 10 (D3)
VRLN
VREF at 60 HZ 525 LINES(1)
0
1
Length
Line number
Field 1
Field 2
240
first
last
19 (22) 258 (261)
282 (285) 521 (524)
242
first
last
18 (21) 259 (262)
281 (284) 522 (525)
Note
1. The numbers given in parenthesis refer to CCIR line counting.
VREF at 50 HZ 625 LINES
0
1
286
first
last
24
309
337
622
288
first
last
23
310
336
623
Table 28 Fine position of HS HDEL0 and HDEL1 SA 10
FINE POSITION OF HS WITH A STEP SIZE
OF 2/LLC
0
1
2
3
CONTROL BITS D5 and D4
HDEL1
0
0
1
1
HDEL0
0
1
0
1
Table 29 Output format selection OFTS0 and OFTS1 SA 10
FORMATS
RGB 565, RGB 888 (dependent on control
bit RGB888) see Table 31
YUV 422 16 bits
YUV 411 12 bits
YUV CCIR-656 8 bits
CONTROL BITS D7 and D6
OFTS1
0
OFTS0
0
0
1
1
0
1
1
1998 May 15
46