Philips Semiconductors
Video Input Processor (VIP)
Product specification
SAA7111
Table 4 Power-on control sequence
INTERNAL POWER-ON
CONTROL SEQUENCE
PIN OUTPUT STATUS
Directly after power-on
asynchronous reset
VPO15 to VPO0, RTCO, RTS0, RTS1,
GPSW, HREF, VREF, HS, VS, LLC, LLC2
and CREF are in high-impedance state
Synchronous reset
sequence
LLC, LLC2, CREF, RTCO, RTS0, RTS1,
GPSW and SDA become active;
VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state
Status after power-on
control sequence
VPO15 to VPO0, HREF, VREF, HS and VS
are held in high-impedance state
FUNCTION
direct switching to high impedance for
20 to 200 ms
internal reset sequence
after power-on (reset sequence) a complete
I2C-bus transmission is required
14 OUTPUT FORMATS
Table 5 Output formats
BUS SIGNAL
VPO15
VPO14
VPO13
VPO12
VPO11
VPO10
VPO9
VPO8
VPO7
VPO6
VPO5
VPO4
VPO3
VPO2
VPO1
VPO0
Pixel order Y
Pixel order UV
Data rates
I2C-bus
control signals
411 (12-BIT)
Y07 Y17 Y27 Y37
Y06 Y16 Y26 Y36
Y05 Y15 Y25 Y35
Y04 Y14 Y24 Y34
Y03 Y13 Y23 Y33
Y02 Y12 Y22 Y32
Y01 Y11 Y21 Y31
Y00 Y10 Y20 Y30
U07 U05 U03 U01
U06 U04 U02 U00
V07 V05 V03 V01
V06 V04 V02 V00
XXXX
XXXX
XXXX
XXXX
0123
0
LLC2
OFTS0 = 0
OFTS1 = 1
RGB888 = X
422 (16-BIT)(1)
Y07
Y17
Y06
Y16
Y05
Y15
Y04
Y14
Y03
Y13
Y02
Y12
Y01
Y11
Y00
Y10
U07
V07
U06
V06
U05
V05
U04
V04
U03
V03
U02
V02
U01
V01
U00
V00
0
1
0
LLC2
OFTS0 = 1
OFTS1 = 0
RGB888 = X
CCIR-656 (8-BIT)(2)
U07 Y07 V07 Y17
U06 Y06 V06 Y16
U05 Y05 V05 Y15
U04 Y04 V04 Y14
U03 Y03 V03 Y13
U02 Y02 V02 Y12
U01 Y01 V01 Y11
U00 Y00 V00 Y10
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
0
1
0
LLC
OFTS0 = 1
OFTS1 = 1
RGB888 = X
RGB (16-BIT)(3)
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
B3
B2
B1
B0
−
−
LLC2
OFTS0 = 0
OFTS1 = 0
RGB888 = 0
RGB (24-BIT)(3)
R7
R7
R6
R6
R5
R5
R4
R4
R3
R3
G7
G7
G6
G6
G5
G5
G4
R2
G3
R1
G2
R0
B7
G1
B6
G0
B5
B2
B4
B1
B3
B0
note 4 note 5
−
LLC
OFTS0 = 0
OFTS1 = 0
RGB888 = 1
Notes
1. Values in accordance with CCIR-601.
2. Before and after the video data, video timing codes are inserted in accordance with CCIR-656.
3. Values not defined during HREF = LOW.
4. CREF = 0 (see Fig.14).
5. CREF = 1 (see Fig.14).
1998 May 15
32