SAA7111 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

SAA7111

Video input processor (VIP).

Philips Electronics 

Philips Semiconductors

Video Input Processor (VIP)

Product specification

SAA7111

handbook, full pagewidth

HIGH

128

BIT NO.:

LOW

15

transmitted once per line

SEQUENCE

INCRHPLL

16

2

INCRFSCPLL

45

DTO RESET(1)

RESERVED

50 Hz fields: 235

60 Hz fields: 232

31

0 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIME SLOT: 0 1

16 19

63 67 68

MGC649

(1) Set to zero for one transmission, if a phase reset of the fsc - DTO is applied via I2C-bit CDTO. RTCO sequence is generated in LLC/4.

The HPLL increment represents the actual LFCO frequency (fLFCO × 4 = fLLC); 16 LSB from 20, upper four bits are fixed to 0100b

fLFCO = I---N--2--C--w---oR--r--d-H---lP-e--n-L--g-L-t-h--×--D--f-T-X--O--T-2--A---L-

Where: fXTAL = 24.576 MHz, word length DTO2 = 20 bits.

The fsc increment represents the actual subcarrier frequency (related to the actual clock); 23 LSB from 24, MSB is 0b.

fsc = I---N----C-2----wR---o--Fr--d-S---lC-e--n-P--g-L-t-h-L---D-×--T---fO--X--1-T---A---L- × -I--N----C---2--R--1---9H---P----L---L

Where: word length DTO1 = 24 bits.

Fig.16 Real time control output.

handbook, full pagewidth LLC

CREF

HREF

FEI

VPO

tSU;DAT

tHD;DAT

tPDZ

tOHD;DAT

tPD

to 3-state

from 3-state

MGC657

Timing is compatible with SAA7110; I2C-bit FECO = 0.

Fig.17 FEI timing diagram (FEI sampling at CREF = LOW).

1998 May 15

25

Share Link: