MTB33N10E View Datasheet(PDF) - Motorola => Freescale
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Description
Manufacturer
MTB33N10E Datasheet PDF : 8 Pages
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COMMUTATING SAFE OPERATING AREA (CSOA)
MTP3N50E
The Commutating Safe Operating Area (CSOA) of
Figure 12 defines the limits of safe operation for commutated
source-drain current versus re-applied drain voltage when
the source-drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VR for a given
commutation speed. It is applicable when waveforms similar
to those of Figure 11 are present. Full or half-bridge PWM DC
motor controllers are common applications requiring CSOA
data.
The time interval tfrr is the speed of the commutation cycle.
Device stresses increase with commutation speed, so tfrr is
specified with a minimum value. Faster commutation speeds
require an appropriate derating of IFM, peak VR or both. Ulti-
mately, tfrr is limited primarily by device, package, and circuit
impedances. Maximum device stress occurs during trr as the
diode goes from conduction to reverse blocking.
VDS(pk) is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum for-
ward source-drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances, Li in Motorola’s test circuit are assumed
to be practical minimums.
4
3
2
di/dt ≤ 50 A/µs
15 V
VGS
0
90%
IS
10%
IFM
dls/dt
trr
ton
IRM
0.25 IRM
VDS(pk)
VR
VDS
dVDS/dt
Vf
VdsL
MAX. CSOA
STRESS AREA
Figure 11. Commutating Waveforms
RGS
DUT
–
VR
+
VGS
IFM
IS
Li
+
VDS
20 V
–
VR = 80% OF RATED VDS
VdsL = Vf + Li ⋅ dls/dt
1
Figure 13. Commutating Safe Operating Area
Test Circuit
0
0
100
200
300
400
500
600
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 12. Commutating Safe Operating Area (CSOA)
V(BR)DSS
Vds(t)
IO
L
VDS
C
ID
4700 µF
250 V
VDD
t
RGS
50 Ω
Figure 14. Unclamped Inductive Switching
Test Circuit
ID(t)
VDD
+ ǒ Ǔ ǒ Ǔ tP
WDSR
t, (TIME)
1
2
L
IO2
V(BR)DSS
V(BR)DSS – VDD
Figure 15. Unclamped Inductive Switching
Waveforms
Motorola TMOS Power MOSFET Transistor Device Data
5
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