TEA1610P View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

TEA1610P

Zero-voltage-switching resonant converter controller

Philips Electronics 

Philips Semiconductors

Zero-voltage-switching

resonant converter controller

Product specification

TEA1610P; TEA1610T

Error amplifier

The error amplifier is a transconductance amplifier. Thus

the output current at pin VCO is determined by the

amplifier transconductance and the differential voltage on

input pins I+ and I−. The output current IVCO is fed to the

IRS input of the current-controlled oscillator.

The source capability of the error amplifier increases

current in the IRS pin when the differential input voltage is

positive. Therefore the minimum current is determined by

resistor Rf(min) and the minimum frequency setting is

independent of the characteristics of the error amplifier.

The error amplifier has a maximum output current of

0.5 mA for an output voltage up to 2.5 V. If the source

current decreases, the oscillator frequency also decreases

resulting in a higher regulated output voltage.

During start-up, the output voltage of the amplifier is held

at a constant value of 2.5 V. This voltage level defines,

together with resistor R∆f, the initial switching frequency of

the TEA1610 after start-up.

Shut-down

The shut-down input (SD) has an accurate threshold level

of 2.33 V. When the voltage on input SD reaches 2.33 V,

both power switches immediately switch off and the

TEA1610 enters shut-down mode.

During shut-down mode, pin VDD is clamped by an internal

Zener diode at 12.0 V with 1 mA input current. This clamp

prevents VDD rising above the rating of 14 V due to low

supply current to the TEA1610 in shut-down mode.

When the TEA1610 is in the shut-down mode, it can be

activated again only by lowering VDD below the VDD reset

level (5.3 V typical). The shut-down latch is then reset and

a new start-up cycle can commence (see Fig.8).

handbook, full pagewidth

2001 Apr 25

oscillation

shut-

down

VDD

supply

off

start-up

oscillation

VDD(start)

VDD(sdc)

VDD(reset)

SD

VSD(th)

GH - SH

0

GL

0

t

MGW002

Fig.8 Shut-down.

8

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