AD7834ARZ1 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7834ARZ1 Datasheet PDF : 28 Pages
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LC2MOS
Quad 14-Bit DACs
AD7834/AD7835
FEATURES
Four 14-bit DACs in one package
AD7834—serial loading
AD7835—parallel 8-bit/14-bit loading
Voltage outputs
Power-on reset function
Maximum/minimum output voltage range of ±8.192 V
Maximum output voltage span of 14 V
Common voltage reference inputs
User-assigned device addressing
Clear function to user-defined voltage
Surface-mount packages
AD7834—28-lead SOIC and PDIP
AD7835—44-lead MQFP and PLCC
APPLICATIONS
Process control
Automatic test equipment
General-purpose instrumentation
GENERAL DESCRIPTION
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output
voltages in the range ±8.192 V with a maximum span of 14 V.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading 0s,
into one via DIN, SCLK, and FSYNC. The AD7834 has five
dedicated package address pins, PA0 to PA4, that can be wired
to AGND or VCC to permit up to 32 AD7834s to be individually
addressed in a multipackage application.
The AD7835 can accept either 14-bit parallel loading or double-
byte loading, where right-justified data is loaded in one 8-bit
byte and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF, and DAC channel address pins, A0 to A2.
With each device, the LDAC signal is used to update all four
DAC outputs simultaneously, or individually, on reception of
new data. In addition, for each device, the asynchronous CLR
input can be used to set all signal outputs, VOUT1 to VOUT4, to
the user-defined voltage level on the device sense ground pin,
DSG. On power-on, before the power supplies have stabilized,
internal circuitry holds the DAC output voltage levels to within
±2 V of the DSG potential. As the supplies stabilize, the DAC
output levels move to the exact DSG potential (assuming CLR is
exercised).
The AD7834 is available in a 28-lead 0.3" SOIC package and a
28-lead 0.6" PDIP package, and the AD7835 is available in a
44-lead MQFP package and a 44-lead PLCC package.
PAEN
PA0
PA1
PA2
PA3
PA4
FSYNC
DIN
SCLK
VCC VDD VSS
FUNCTIONAL BLOCK DIAGRAMS
VREF(–) VREF(+)
VCC VDD VSS
VREF(–)A VREF(+)A DSGA
AD7834
INPUT
REGISTER
1
DAC 1
LATCH
DAC 1
×1
CONTROL
INPUT
REGISTER
2
DAC 2
LATCH
DAC 2
LOGIC
×1
AND
ADDRESS
DECODE
INPUT
REGISTER
3
DAC 3
LATCH
DAC 3
×1
SERIAL-TO-
PARALLE L
INPUT
REGISTER
4
DAC 4
LATCH
DAC 4
CONVERTER
×1
AGND DGND LDAC
DSG
Figure 1. AD7834
VOUT 1
VOUT 2
VOUT 3
VOUT 4
CLR
BYSHF
DB13
DB0
WR
CS
A0
A1
A2
AD7835
INPUT 14
BUFFER
ADDRESS
DECODE
INPUT
REGISTER
1
DAC 1
LATCH
INPUT
REGISTER
2
DAC 2
LATCH
INPUT
REGISTER
3
DAC 3
LATCH
INPUT
REGISTER
4
DAC 4
LATCH
DAC 1
DAC 2
DAC 3
DAC 4
×1
VOUT1
×1
VOUT2
×1
VOUT3
×1
VOUT4
CLR
AGND
DGND LDAC VREF(–)B VREF(+)B DSGB
Figure 2. AD7835
Rev. D
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
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Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
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