FW32305 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

FW32305

1394A PCI PHY/Link Open Host Controller Interface

Agere -> LSI Corporation 

Data Sheet, Rev. 2

October 2001

FW323 05

1394A PCI PHY/Link Open Host Controller Interface

FW323 Functional Overview

s PCI:

— Revision 2.2 compliant

— 33 MHz/32-bit operation

— Programmable burst size for PCI data transfer

— Supports PCI Bus Power Management Interface Specification v.1.1

— Supports clockrun protocol per PCI Mobile Design Guide

— Global byte swap function

Other Features

s I2C serial ROM interface

s CMOS process

s 3.3 V operation, 5 V tolerant inputs

s 128-pin TQFP package

The FW323 is the Agere Systems Inc. implementation of a high-performance, PCI bus-based open host controller for

implementation of IEEE 1394a-2000 compliant systems and devices. Link-layer functions are handled by the

FW323, utilizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and cost-

effective solution for connecting and servicing multiple IEEE 1394 (both 1394-1995 and 1394a-2000) peripheral

devices can be realized.

PCI

BUS

PCI

CORE

ROM

I/F

OHCI

ASYNC

OHCI

ISOCH

LINK

CORE

PHY

CORE

CABLE PORT 2

CABLE PORT 1

CABLE PORT 0

Figure 1. FW323 Functional Block Diagram

5-6250 (F).e

FW323 Functional Description

The FW323 is comprised of five major functional

sections (see Figure 1): PCI core, isochronous data

transfer, asynchronous data transfer, link core, and

PHY core. The following is a general description of

each of the five major sections.

PCI Core

The PCI core serves as the interface to the PCI bus. It

contains the state machines that allow the FW323 to

respond properly when it is the target of the transaction.

During 1394 packet transmission or reception, the PCI

core arbitrates for the PCI bus and enables the FW323

Agere Systems Inc.

to become the bus master for reading the different

buffer descriptors and management of the actual data

transfers to/from host system memory.

The PCI core also supports the PCI Bus Power

Management Interface Specification v.1.1. Included in

this support is a standard power management register

interface accessible through the PCI configuration

space. Through this register interface, software is able

to transition the FW323 into four distinct power

consumption states (D0, D1, D2, and D3). This permits

software to selectively increase/decrease the power

consumption of the FW323 for reasons such as periods

of system inactivity or power conservation. In addition,

the FW323 also includes support for hardware wake-up

mechanisms through power management events

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