FW322 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name

Description

Manufacturer

FW322

1394A PCI PHY/Link Open Host Controller Interface

Agere -> LSI Corporation 

FW322

1394A PCI PHY/Link Open Host Controller Interface

Data Sheet, Rev. 1

February 2001

Table of Contents (continued)

Table

Page

Table 1. Pin Descriptions ....................................................................................................................................... 13

Table 2. Bit-Field Access Tag Description ............................................................................................................. 19

Table 3. PCI Configuration Register Map .............................................................................................................. 19

Table 4. Vendor ID Register .................................................................................................................................. 20

Table 5. Device ID Register ................................................................................................................................... 21

Table 6. PCI Command Register ........................................................................................................................... 22

Table 7. PCI Command Register Description ........................................................................................................ 23

Table 8. PCI Status Register ................................................................................................................................. 24

Table 9. Class Code and Revision ID Register .................................................................................................... 25

Table 10. Class Code and Revision ID Register Description ................................................................................ 26

Table 11. Latency Timer and Class Cache Line Size Register ............................................................................. 26

Table 12. Latency Timer and Class Cache Line Size Register Description ......................................................... 27

Table 13. Header Type and BIST Register ........................................................................................................... 27

Table 14. Header Type and BIST Register Description ........................................................................................ 28

Table 15. OHCI Base Address Register ................................................................................................................ 29

Table 16. OHCI Base Address Register Description ............................................................................................. 30

Table 17. PCI Subsystem Identification Register Description ............................................................................... 31

Table 18. PCI Power Management Capabilities Pointer Register ......................................................................... 31

Table 19. Interrupt Line and Pin Register .............................................................................................................. 32

Table 20. Interrupt Line and Pin Register Description ........................................................................................... 32

Table 21. MIN_GNT and MAX_LAT Register ........................................................................................................ 33

Table 22. MIN_GNT and MAX_LAT Register Description ..................................................................................... 33

Table 23. PCI OHCI Control Register ................................................................................................................... 34

Table 24. PCI OHCI Control Register Description ................................................................................................. 35

Table 25. Capability ID and Next Item Pointer Register ........................................................................................ 36

Table 26. Capability ID and Next Item Pointer Register Description ..................................................................... 36

Table 27. Power Management Capabilities Register ............................................................................................ 37

Table 28. Power Management Capabilities Register Description ......................................................................... 38

Table 29. Power Management Control and Status Register ................................................................................ 39

Table 30. Power Management Control and Status Register Description .............................................................. 40

Table 31. Power Management Extension Register ............................................................................................... 41

Table 32. Power Management Extension Register Description ........................................................................... 41

Table 33. OHCI Register Map ............................................................................................................................... 42

Table 34. OHCI Version Register .......................................................................................................................... 45

Table 35. OHCI Version Register Description ....................................................................................................... 46

Table 36. GUID ROM Register ............................................................................................................................. 47

Table 37. GUID ROM Register Description ........................................................................................................... 48

Table 38. Asynchronous Transmit Retries Register ............................................................................................. 49

Table 39. Asynchronous Transmit Retries Register Description ........................................................................... 50

Table 40. CSR Data Register ................................................................................................................................ 51

Table 41. CSR Data Register Description ............................................................................................................. 52

Table 42. CSR Compare Register ......................................................................................................................... 53

Table 43. CSR Compare Register Description ...................................................................................................... 54

Table 44. CSR Control Register ............................................................................................................................ 55

Table 45. CSR Control Register Description ........................................................................................................ 56

Table 46. Configuration ROM Header Register ..................................................................................................... 57

Table 47. Configuration ROM Header Register Description ................................................................................. 58

Table 48. Bus Identification Register ..................................................................................................................... 59

Table 49. Bus Identification Register Description .................................................................................................. 60

Table 50. Bus Options Register ............................................................................................................................. 61

Table 51. Bus Options Register Description .......................................................................................................... 62

4

Lucent Technologies Inc.

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