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FW322 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name
Description
Manufacturer
FW322 Datasheet PDF : 148 Pages
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FW322
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 1
February 2001
FW322 Functional Description (continued)
recover the receive clock signal and the serial data bits.
The serial data bits are split into two, four, or eight par-
allel streams, resynchronized to the local system clock,
and sent to the associated LLC. The received data is
also transmitted (repeated) out of the other active (con-
nected) cable ports.
Both the TPA and TPB cable interfaces incorporate
differential comparators to monitor the line states during
initialization and arbitration. The outputs of these
comparators are used by the internal logic to determine
the arbitration status. The TPA channel monitors the
incoming cable common-mode voltage. The value of
this common-mode voltage is used during arbitration to
set the speed of the next packet transmission. In
addition, the TPB channel monitors the incoming cable
common-mode voltage for the presence of the remotely
supplied twisted-pair bias voltage. This monitor is called
bias-detect.
The TPBIAS circuit monitors the value of incoming TPA
pair common-mode voltage when local TPBIAS is
inactive. Because this circuit has an internal current
source and the connected node has a current sink, the
monitored value indicates the cable connection status.
The monitor is called connect-detect.
Both the TPB bias-detect monitor and TPBIAS connect-
detect monitor are used in suspend/resume signaling
and cable connection detection.
The PHY core provides a 1.86 V nominal bias voltage
for driver load termination. This bias voltage, when
seen through a cable by a remote receiver, indicates
the presence of an active connection. The value of this
bias voltage has been chosen to allow interoperability
between transceiver chips operating from 5 V or 3 V
nominal supplies. This bias voltage source should be
stabilized by using an external filter capacitor of
approximately 0.33 µF.
The port transmitter circuitry and the receiver circuitry
are disabled when the port is disabled, suspended, or
disconnected.
The line drivers in the PHY core operate in a high-
impedance current mode and are designed to work with
external 112 line-termination resistor networks. One
network is provided at each end of each twisted-pair
cable. Each network is composed of a pair of series-
connected 56 resistors. The midpoint of the pair of
resistors that is directly connected to the twisted-pair A
(TPA) signals is connected to the TPBIAS voltage
signal. The midpoint of the pair of resistors that is
directly connected to the twisted-pair B (TPB) signals is
coupled to ground through a parallel RC network with
recommended resistor and capacitor values of 5 k
and 220 pF, respectively. The value of the external
resistors are specified to meet the draft standard
specifications when connected in parallel with the
internal receiver circuits.
The driver output current, along with other internal
operating currents, is set by an external resistor. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 k±1%.
Four signals are used as inputs to set four configuration
status bits in the self-identification (self-ID) packet.
These signals are hardwired high or low as a function
of the equipment design. PC[0:2] are the three signals
that indicate either the need for power from the cable or
the ability to supply power to the cable. The fourth
signal (CONTENDER) as an input indicates whether a
node is a contender for bus manager. When the
CONTENDER signal is asserted, it means the node is a
contender for bus manager. When the signal is not
asserted, it means that the node is not a contender.
The contender bit corresponds to bit 20 in the self-ID
packet, PC0 corresponds to bit 21, PC1 corresponds to
bit 22, and PC2 corresponds to bit 23 (see Table 4-29
of the IEEE 1394-1995 standard for additional details).
When the power supply of the PHY core is removed
while the twisted-pair cables are connected, the PHY
core transmitter and receiver circuitry has been
designed to present a high impedance to the cable in
order to not load the TPBIAS signal voltage on the
other end of the cable.
For reliable operation, the TPBn signals must be
terminated using the normal termination network
regardless of whether a cable is connected to port or
not connected to a port. For those applications, when
FW322 is used with one or more of the ports not
brought out to a connector, those unused ports may be
left unconnected without normal termination. When a
port does not have a cable connected, internal connect-
detect circuitry will keep the port in a disconnected
state.
Note: All gap counts on all nodes of a 1394 bus must
be identical. This may be accomplished by using
PHY core configuration packets (see Section
4.3.4.3 of IEEE 1394-1995 standard) or by using
two bus resets, which resets the gap counts to
the maximum level (3Fh).
The internal link power status (LPS) signal works with
the internal LinkOn signal to manage the LLC power
usage of the node. The LPS signal indicates that the
LLC of the node is powered up or down. If LPS is
inactive for more than 1.2 µs and less than 25 µs, the
internal PHY/link interface is reset.
If LPS is inactive for greater than 25 µs, the PHY will
disable the internal PHY/link interface to save power.
10
Lucent Technologies Inc.
 

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