EVAL-ADE7759EB View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

EVAL-ADE7759EB

Active Energy Metering IC with di/dt Sensor Interface

Analog Devices 

ADE7759

TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = 5 V ؎ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz

XTAL, TMIN to TMAX = –40؇C to +85؇C, unless otherwise noted.)

Parameter

A, B Versions Unit

Test Conditions/Comments

Write Timing

t1

20

t2

150

t3

150

t4

10

t5

5

t6

6.4

t7

4

t8

100

Read Timing

t9

4

t10

4

t113

30

t124

100

10

t134

100

10

ns (min)

ns (min)

ns (min)

ns (min)

ns (min)

ms (min)

ms (min)

ns (min)

CS Falling Edge to First SCLK Falling Edge

SCLK Logic High Pulsewidth

SCLK Logic Low Pulsewidth

Valid Data Setup Time before Falling Edge of SCLK

Data Hold Time after SCLK Falling Edge

Minimum Time between the End of Data Byte Transfers

Minimum Time between Byte Transfers during a Serial Write

CS Hold Time after SCLK Falling Edge

ms (min)

ms (min)

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

Minimum Time between Read Command (i.e., a Write to Communications

Register) and Data Read

Minimum Time between Data Byte Transfers during a Multibyte Read

Data Access Time after SCLK Rising Edge following a Write to the Communica-

tions Register

Bus Relinquish Time after Falling Edge of SCLK

Bus Relinquish Time after Rising Edge of CS

NOTES

1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns

(10% to 90%) and timed from a voltage level of 1.6 V.

2See Figures 2 and 3 and Serial Interface section of this data sheet.

3Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of

the part and is independent of the bus loading.

REV. A

CS

t1

SCLK

DIN

CS

t1

SCLK

DIN

DOUT

200␮A

IOL

TO

OUTPUT

PIN

CL

50pF

2.1V

1.6mA

IOH

Figure 1. Load Circuit for Timing Specifications

t8

t2

t3

t7

t4

t5

1 0 0 A4 A3 A2 A1 A0

DB7

t6

t7

DB0

DB7

DB0

COMMAND BYTE

MOST SIGNIFICANT BYTE

Figure 2. Serial Write Timing

LEAST SIGNIFICANT BYTE

t9

t10

t13

0 0 0 A4 A3 A2 A1 A0

t11

DB7

t11

DB0

DB7

t12

DB0

COMMAND BYTE

MOST SIGNIFICANT BYTE

Figure 3. Serial Read Timing

LEAST SIGNIFICANT BYTE

–5–

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