MTV018N View Datasheet(PDF) - Myson Century Inc

Part Name

Description

Manufacturer

MTV018N

Super On-Screen-Display

Myson Century Inc 

MYSON

TECHNOLOGY

MTV018

cal display height control register(CH6-CH0).The algorithm of repeating character line display are shown as

Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.

The vertical display center for full screen display could be figured out according to the information of vertical

starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,

is calculated with the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H

TABLE 2. Repeat line weight of character

CH6 - CH0

CH6,CH5=11

CH6,CH5=10

CH6,CH5=0x

CH4=1

CH3=1

CH2=1

CH1=1

CH0=1

Repeat Line Weight

+18*3

+18*2

+18

+16

+8

+4

+2

+1

Where H = one horizontal line display time

TABLE 3. Repeat line number of character

Repeat Line

Repeat Line #

Weight

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

+1

-- --- -- -v- -- --- -- -

+2

----v-- --- --v-- ---

+4

--v-- -v---v- --v-- -

+8

-v-v-v-v-v-v-v-v- -

+16

- vvvvvvvvvvvvvvvv -

+17

vvvvvvvvvvvvvvvvv -

+18

vvvvvvvvvvvvvvvvvv

Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the

character would not be repeated.

3.4 Horizontal display control

The horizontal display control is used to generate control timing for horizontal display based on double char-

acter width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and

HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display char-

acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calcu-

lated with the following equation,

Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width

Where P = One pixel display time = One horizontal line display time / (HORR*12)

3.5 Phase lock loop (PLL)

On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution reg-

ister (HORR). The frequency of VCLK is determined by the following equation:

6/16

MTV018 Revision 4.0 10/21/1999

Share Link: