U631H64BDC25G1 View Datasheet(PDF) - Zentrum Mikroelektronik Dresden AG
Part Name
Description
Manufacturer
U631H64BDC25G1 Datasheet PDF : 12 Pages
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U631H64
No. Software Controlled STORE/RECALL
Cyclel, n
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactiveo
27 STORE Cycle Timep
28 RECALL Cycle Timeq
29 Address Setup to Chip Enabler
30 Chip Enable Pulse Widthr, s
31 Chip Disable to Address Changer
Symbol
Alt.
IEC
tAVAV
tELQZ
tELQXS
tELQXR
tAVELN
tELEHN
tEHAXN
tcR
tdis(E)SR
td(E)S
td(E)R
tsu(A)SR
tw(E)SR
th(A)SR
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
25
35
45
ns
600
600
600 ns
10
10
10 ms
20
20
20 µs
0
0
0
ns
20
25
35
ns
0
0
0
ns
n: The software sequence is clocked with E controlled READs.
o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
q: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
r: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
Software Controlled STORE/RECALL Cycler, s, t, u (E = HIGH after STORE initiation)
Ai
E
DQi
Output
tcR (25)
ADDRESS 1
tsu(A)SR (29)
tw(E)SR
(30)
(31) th(A)SR
High Impedance
VALID
tcR (25)
ADDRESS 6
(29)
tsu(A)SR
tw(E)SR
(30)
(31) th(A)SR
tdis(E)(5)
td(E)S (27) td(E)R (28)
VALID
tdis(E)SR (26)
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
Ai
E
DQi
Output
tcR (25)
ADDRESS 1
tsu(A)SR (29)
tw(E)SR
(30)
(31) th(A)SR
High Impedance
VALID
ADDRESS 6
th(A)SR (31)
(29)
tsu(A)SR
td(E)S (27) td(E)R (28)
VALID
tdis(E)SR (26)
t: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U631H64 performs a STORE
or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
8
April 20, 2004
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