U631H256CSC25 View Datasheet(PDF) - Zentrum Mikroelektronik Dresden AG
Part Name
Description
Manufacturer
U631H256CSC25 Datasheet PDF : 12 Pages
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U631H256
Symbol
No. Software Controlled STORE/RECALL
Cyclel, n
Alt.
IEC
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
25 STORE/RECALL Initiation Time
26 Chip Enable to Output Inactiveo
27 STORE Cycle Timep
28 RECALL Cycle Timeq
29 Address Setup to Chip Enabler
30 Chip Enable Pulse Widthr, s
31 Chip Disable to Address Changer
tAVAV
tcR
25
35
45
ns
tELQZ tdis(E)SR
600
600
600 ns
tELQXS td(E)S
10
10
10 ms
tELQXR td(E)R
20
20
20 µs
tAVELN tsu(A)SR 0
0
0
ns
tELEHN tw(E)SR 20
25
30
ns
tEHAXN th(A)SR
0
0
0
ns
n: The software sequence is clocked with E controlled READs
o: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
p: Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
q: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
r: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
s: If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
SOFTWARE CONTROLLED STORE/RECALL CYCLEt, u (E = HIGH after STORE initiation)
25
Ai
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tcR
ADDRESS 1
30
E
29
tsu(A )SR
tw(E)SR
31
th(A )SR
25
tcR
ADDRESS 6
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
27 / 28
td(E)S / td(E)R
DQi
Output
High Impedance VALID
VALID
26
tdis(E)SR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
SOFTWARE CONTROLLED STORE/RECALL CYCLEr, s, t, u (E = LOW after STORE initiation)
25
tcR
Ai
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
ADDRESS 1
E
30
29
tw(E)SR
31
tsu(A )SR
th(A)SR
DQi
Output
High Impedance VALID
29
tsu(A )SR
ADDRESS 6
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
31
th(A)SR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
27 / 28
td(E)S / td(E)R
VALI D
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
26
tdis(E)SR
t: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the U631H256 performs a STORE
or RECALL.
u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
8
December 12, 1997
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