28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
2. Since each column lists specifications for a different VCC and VCCQ voltage range combination, the test
conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ
voltage listed at the top of each column. VCCMax is 3.3 V on 0.25µm 32-Mbit devices.
3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation.
4. Sampled, not 100% tested.
5. Erase and program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of
VPP1, VPP2, VPP3 and VPP4. For read operations or during idle time, a 5 V supply may be applied to VPP
indefinitely. However, VPP must be at valid levels for program and erase operations.
6. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the
main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours
maximum. See Section 3.4 for details. For read operations or during idle time, a 5 V supply may be applied to
VPP indefinitely. However, VPP must be at valid levels for program and erase operations.
Figure 5. Input/Output Reference Waveform
VCCQ
0.0
INPUT
VCCQ
2
TEST POINTS
VCCQ OUTPUT
2
0580_05
NOTE: AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output
timing ends, at VCCQ/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are
when VCCQ = VCCQMin.
Figure 6. Test Configuration
VCCQ
R1
Device
under
Out
Test
CL
R2
NOTE: See table for component values.
Test Configuration Component Values for Worst
Case Speed Conditions
Test Configuration
VCCQ1 Standard Test
VCCQ2 Standard Test
VCCQ3 Standard Test
CL (pF)
50
50
50
R1 (Ω)
25 K
14.5 K
16 K
NOTE: CL includes jig capacitance.
R2 (Ω)
25 K
14.5 K
16 K
0580_06
22
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