GE28F640B3B110 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

GE28F640B3B110

3 Volt Advanced Boot Block Flash Memory

Intel 

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Table 7. Status Register Bit Definition

WSMS

ESS

ES

PS

VPPS

PSS

BLS

R

7

6

5

4

3

2

1

0

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase In Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error In Block Erasure

0 = Successful Block Erase

SR.4 = PROGRAM STATUS (PS)

1 = Error in Word Program

0 = Successful Word Program

SR.3 = VPP STATUS (VPPS)

1 = VPP Low Detect, Operation Abort

0 = VPP OK

SR.2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

0 = Program in Progress/Completed

SR.1 = BLOCK LOCK STATUS

1 = Program/Erase attempted on locked block;

Operation aborted

0 = No operation to locked blocks

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES:

Check Write State Machine bit first to determine word program

or block erase completion, before checking program or erase

status bits.

When erase suspend is issued, WSM halts execution and sets

both WSMS and ESS bits to “1.” ESS bit remains set at “1” until

an Erase Resume command is issued.

When this bit is set to “1,” WSM has applied the max. number

of erase pulses to the block and is still unable to verify

successful block erasure.

When this bit is set to “1,” WSM has attempted but failed to

program a word.

The VPP status bit does not provide continuous indication of

VPP level. The WSM interrogates VPP level only after the

Program or Erase command sequences have been entered,

and informs the system if VPP has not been switched on. The

VPP is also checked before the operation is verified by the

WSM. The VPP status bit is not guaranteed to report accurate

feedback between VPPLK max and VPP1 min or between VPP1

max and VPP4 min.

When program suspend is issued, WSM halts execution and

sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”

until a Program Resume command is issued.

If a program or erase operation is attempted to one of the

locked blocks, this bit is set by the WSM. The operation

specified is aborted and the device is returned to read status

mode.

This bit is reserved for future use and should be masked out

when polling the status register.

NOTE: A Command Sequence Error is indicated when both SR.4, SR.5 and SR.7 are set.

3.3

3.3.1

Block Locking

The 3 Volt Advanced Boot Block flash memory architecture features two hardware-lockable

parameter blocks.

WP# = VIL for Block Locking

The lockable blocks are locked when WP# = VIL; any program or erase operation to a locked block

will result in an error, which will be reflected in the status register. For top configuration, the top

two parameter blocks (blocks #133 and #134 for the 64 Mbit, #69 and #70 for the 32 Mbit, blocks

#37 and #38 for the 16 Mbit, blocks #21 and #22 for the 8 Mbit, blocks #13 and #14 for the 4 Mbit)

are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for

4 /8 /16 /32/64 Mbit) are lockable. Unlocked blocks can be programmed or erased normally (unless

VPP is below VPPLK).

14

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