|Description||3 Volt Advanced Boot Block Flash Memory|
|GE28F400B3BC90 Datasheet PDF : 58 Pages |
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
When the status register indicates that erasure is complete, check the erase status bit to verify that
the erase operation was successful. If the erase operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase failure. If VPP was not within acceptable limits after
the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,
SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to identify that
VPP supply voltage was not within acceptable limits.
After an erase operation, clear the status register (50H) before attempting the next operation. Any
CUI instruction can follow after erasure is completed; however, to prevent inadvertent status
register reads, it is advisable to place the flash in read array mode after the erase is complete.
188.8.131.52 Suspending and Resuming Erase
Since an erase operation requires on the order of seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in order to read data from or program data to
another block in memory. Once the erase sequence is started, writing the Erase Suspend command
to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase
algorithm. The status register will indicate if/when the erase operation has been suspended.
A Read Array/Program command can now be written to the CUI in order to read data from/
program data to blocks other than the one currently suspended. The Program command can
subsequently be suspended to read yet another array location. The only valid commands while
erase is suspended are Erase Resume, Program, Read Array, Read Status Register, or Read
Identifier. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking
CE# to VIH. This reduces active current consumption.
Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard erase
operation, the status register must be read and cleared before the next instruction is issued.
Table 6. Command Bus Definitions (1,4)
Read Status Register
Clear Status Register
First Bus Cycle
Second Bus Cycle
PA: Program Address PD: Program Data BA: Block Address
IA: Identifier Address ID: Identifier Data SRD: Status Register Data
1. Bus operations are defined in Table 3.
2. Following the Intelligent Identifier command, two read operations access manufacturer and device codes.
A 0 = 0 for manufacturer code, A0 = 1 for device code. A1–A21 = 0.
3. Either 40H or 10H command is valid although the standard is 40H.
4. When writing commands to the device, the upper data bus [DQ 8–DQ15] should be either VIL or VIH, to
minimize current draw.
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