GE28F640B3T90 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

GE28F640B3T90

3 Volt Advanced Boot Block Flash Memory

Intel 

28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3.2.2

Read Identifier

To read the manufacturer and device codes, the device must be in read identifier mode, which can

be reached by writing the Read Identifier command (90H). Once in read identifier mode, A0 = 0

outputs the manufacturer’s identification code and A0 = 1 outputs the device identifier (see

Table 5) Note: A1–A21 = 0. To return to read array mode, write the Read Array command (FFH).

Table 5. Read Identifier Table

Size

Mfr. ID

28F004B3

28F400B3

28F008B3

28F800B3

28F016B3

28F160B3

28F320B3

28F640B3

0089H

0089H

0089H

Device Identifier

-T

(Top Boot)

D4H

8894H

D2H

8892H

D0H

8890H

8896H

8898H

-B

(Bottom Boot)

D5H

8895H

D3H

8893H

D1H

8891H

8897H

8899H

3.2.3

Read Status Register

The device status register indicates when a program or erase operation is complete and the success

or failure of that operation. To read the status register issue the Read Status Register (70H)

command to the CUI. This causes all subsequent read operations to output data from the status

register until another command is written to the CUI. To return to reading from the array, issue the

Read Array (FFH) command.

The status register bits are output on DQ0–DQ7. The upper byte, DQ8–DQ15, outputs 00H during a

Read Status Register command.

The contents of the status register are latched on the falling edge of OE# or CE#. This prevents

possible bus errors which might occur if status register contents change while being read. CE# or

OE# must be toggled with each subsequent status read, or the status register will not indicate

completion of a program or erase operation.

When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status

register indicate whether or not the WSM was successful in performing the desired operation (see

Table 7 on page 14).

3.2.3.1

Clearing the Status Register

The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear

status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these

bits can only be cleared through the Clear Status Register (50H) command. By allowing the system

software to control the resetting of these bits, several operations may be performed (such as

cumulatively programming several addresses or erasing multiple blocks in sequence) before

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11

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