LC72720 View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

LC72720

Single-chip RDS signal-processing system LSI

SANYO -> Panasonic 

LC72720, 72720M

Mode (PT2 = 0)

The SYNC pin

0 to 2

When synchronized: Low (0). When unsynchronized: High (1)

When synchronized: Goes high for a fixed period (421 µs) at

3

the start of a block and then goes low.

When unsynchronized: High (1)

Caution: The output indicates the synchronization state for the previous block.

When PT2 = 0

No RDS

RDS present

The RDS-ID pin

High (1)

Low (0)

10. Test mode settings (4 bits): TS0 to TS3

Initial values: TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0

(Applications must set these bits to the above values.)

Notes: The T1 and T2 pins (pins 7 and 8) are related to test mode as follows:

Pin T1 Pin T2

LSI operation

Notes

0

0

Normal operating mode

These states are user settable

0

1

Standby mode (crystal oscillator stopped)

1

0/1

LSI test mode

Users cannot use this state

The T1 pin must be tied to VSS (0 V).

11. Circuit control (2 bits): CT0 and CT1

Item

CT0

RSFT control

CT1 RDS-ID detection condition

Initial values: CT0 = 0, CT1 = 0

Control

When set to 1, soft-decision control data (RSFT) is easier to generate.

When set to 1, the RDS-ID detection conditions are made more restrictive.

RDCL/RDDA/RSFT and ERROR/CORREC/SYNC Output Timing

Timing 1 (modes 1 to 3, PT2 = 0)

RDCL output

RDDA output

RSFT output

Note: When PT2 = 0, RDDA and RSFT must be

aquired on the falling edge of RDCL.

Timing 2 (mode 3, PT2 = 0)

Input data

Error crrection

Sync NG Sync OK Sync OK Sync OK Sync OK Sync OK Sync NG Sync NG

Data

No

corrected errors

No

errors

Data

corrected

SYNC output

ERROR output

CORREC output

No. 5602-10/14

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