M38747MCT-XXXG View Datasheet(PDF) - MITSUBISHI ELECTRIC

Part Name

Description

Manufacturer

M38747MCT-XXXG

Single-chip 8-bit CMOS microcomputer. ROM 61440 bytes, RAM 2048 bytes. Mask ROM version.

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

3874 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

q SRDY3 output signal

The SRDY3 output is a transmit/receive enable signal which in-

forms the serial transfer destination that transmit/receive is ready.

In the initial status, that is, when the serial I/O initialization bit (b4)

is reset to “0”, the SRDY3 output goes to “L” and the SRDY3 output

goes to “H”. After transmitted data is stored in the serial I/O3 reg-

ister (address 001316) and a transmit/receive operation becomes

ready, the SRDY3 output goes to “H” and the SRDY3 output goes to

“L”. When a transmit/receive operation is started and the transfer

clock goes to “L”, the SRDY3 output goes to “L” and the SRDY3 out-

put goes to “H”.

q SRDY3 input signal

The SRDY3 input signal becomes valid only when the SRDY3 input

and the SBUSY3 output are used. The SRDY3 input is a signal for re-

ceiving a transmit/receive ready completion signal from the serial

transfer destination.

When the internal synchronous clock is selected, input a low level

signal into the SRDY3 input and a high level signal into the SRDY3

input in the initial status in which the transfer is stopped.

When an “H” level signal is input into the SRDY3 input and an “L”

level signal is input into the SRDY3 input for a period of 1.5 cycles

or more of transfer clock, transfer clocks are output from the SCLK3

output and a transmit/receive operation is started.

After the transmit/receive operation is started and an “L” level sig-

nal is input into the SRDY3 input and an “H” level signal into the

SRDY3 input, this operation cannot be immediately stopped.

After the specified number of bits are transmitted and received,

the transfer clocks from the SCLK3 output is stopped. The hand-

shake unit of the 8-bit serial I/O and that of the automatic transfer

serial I/O are of 8 bits. That of the arbitrary bit serial I/O is the bit

number adding “1” to the set value to the transfer counter.

When the external synchronous clock is selected, the SRDY3 input

becomes one of the triggers to output the SBUSY3 signal.

To start a transmit/receive operation (SBUSY3 output to “L”, SBUSY3

output to “H”), input an “H” level signal into the SRDY3 input and an

“L” level signal into the SRDY3 input, and also write transmit data

into the serial I/O3 register.

SCLK3

Serial I/O3 register

→ Automatic transfer RAM

Automatic transfer RAM

→ Serial I/O3 register

SBUSY3

Serial transfer

status flag

SOUT3

Transfer

interval

Automatic transfer

interval

Fig. 46 SBUSY3 output operation in arbitrary bit serial I/O mode (internal synchronous clock)

Transfer

interval

SRDY3

SCLK3

Write to serial

I/O3 register

Fig. 47 SRDY3 Output Operation

48

SRDY3

SCLK3

SOUT3

Fig. 48 SRDY3 Input Operation (internal synchronous clock)

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