AD9772AASTZRL View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9772AASTZRL

0.3-7V; 14-bit, 160MSPS TxDAC+ with 2X interpolation filter

Analog Devices 

AD9772A

RED

TP16

BLK WHT

TP17 TP5

C5

0.1␮F

AVDD

C6

1␮F

WHT

TP6

AVDD

C4

0.1␮F

R10

1.91k⍀

EXT REF 3

B

REFLO 2A JP4

INT REF 1

RED

TP14

TP15

BLK

c

DVDD

C7

0.1␮F

C8

0.1␮F

1

2

3

MSB DB13

4

DB12

5

DB11

6

DB10

DB9

7

DB8

8

DB7

9

DB6

10

11

DB5

12

DB4

48 47 46 45 44 43 42 41 40 39 38 37

PIN 1

IDENTIFIER

U1

AD9772A

13 14 15 16 17 18 19 20 21 22 23 24

c

CONNECT GNDs AS SHOWN UNDER

USING BOTTOM SIGNAL LAYER

DVDD

3

JP11

B

2

H

L

MOD0

3

JP10

B

2

H

L

TP1

WHT

MOD1

C11 TP3

0.1␮F WHT

C12

1␮F

TP4

WHT

DVDD

1

DGND

1

TP2

WHT

NOTE:

LOCATE ALL DECOUPLING CAPS (C5 – C12) AS CLOSE AS POSSIBLE TO DUT,

PREFERABLY UNDER DUT ON BOTTOM SIGNAL LAYER.

R16

VAL

C3 R8

10pF 50⍀

T2

IA

3

S

R9

OPT

P4

2

6

IB

1

C2 R7

10pF 50⍀

R17

VAL

J6

1

IOUT

2

TP11

SLEEP WHT

36

35 LPF

34

33

32

31

30 CLK–

29 CLK+

28 DIV0

27 DIV1

26

25 PLL-LOCK

1

J1

2

c

TP28

WHT

R6

50⍀

NOTE:

SHIELD AROUND R5, C1

CONNECTED TO PLLVDD

R5 C1

VAL VAL

PLLVDD

C9

C10 CLKVDD

1␮F 0.1␮F

c

RESET

TP10

WHT

CLKVDD

3

B

2A JP5

3

1

TP7 RED

B

2 A JP6 3

1

B

2 A JP7

1

c

WHT

TP12 CLOCK

J3

1

3

2

JP8

EDGE

SE B

DF

2A JP2

CLKVDD 1

JP1

DF

c

CLOCK

R2

1k⍀

T1

1

S

3

SE B

DF 2A JP3

1

R3

1k⍀

c

C19 2

0.1␮F

3

P6

4

c

R1

50⍀

3

DF B

SE2 A JP9

1

c

Figure 38. Drafting Schematic of Evaluation Board (continued)

–26–

REV. A

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