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ADC0838CCN Просмотр технического описания (PDF) - Micro Linear Corporation

Номер в каталогеADC0838CCN Micro-Linear
Micro Linear Corporation Micro-Linear
Компоненты ОписаниеSerial I/O 8-Bit A/D Converters with Multiplexer Options
ADC0838CCN Datasheet PDF : 26 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ML2281, ML2282, ML2284, ML2288
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
TYP
MIN NOTE 3 MAX
LIMIT
UNITS
AC ELECTRICAL CHARACTERISTICS
fCLK
Clock Frequency
(Note 4)
10
tACQ
Sample-and-Hold Acquisition
tC
Conversion Time
Not including MUX adddressing time
SNR
Signal to Noise Ratio
ML2281
VIN = 40kHz, 5V sine. fCLK = 1.333MHz
(fSAMPLING » 120kHz). Noise is sum of all
nonfundamental components up to 1/2
of fSAMPLING (Note 11)
THD
Total Harmonic Distortion
ML2281
VIN = 40kHz, 5V sine. fCLK = 1.333MHz
(fSAMPLING » 120kHz). THD is sum of 2,
3, 4, 5 harmonics relative to fundamental
(Note 11)
1.333
kHz
1/2
1/fCLK
8
1/fCLK
47
dB
–60
dB
IMD
Intermodulation Distortion VIN = fA + fB. fA = 40kHz, 2.5V sine.
–60
dB
ML2281
fB = 39.8kHz, 2.5V Sine, fCLK = 1.333MHz
(fSAMPLING » 120kHz). IMD is (fA + fB),
(fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB),
(fA – 2fB) relative to fundamental (Note 11)
Clock Duty Cycle
(Notes 4, 10)
40
60
%
tSET-UP
CS Falling Edge or Data Input (Note 4)
Valid to CLK Rising Edge
130
ns
tHOLD
Data Input Valid after
CLK Rising Edge
(Note 4)
80
ns
tPD1,
tPD0
CLK Falling Edge to Output
Data Valid
CL = 100pF (Note 4 & 12)
Data MSB first
Data LSB first
90
200
ns
50
110
ns
t1H,
t0H
CIN
COUT
Rising Edge of CS to Data
Output and SARS Hi-Z
CL = 10pF, RL = 10k (see high impedance
test circuits) (Note 5)
Capacitance of Logic Input
CL = 100pF, RL = 2k (Note 4)
Capacitance of Logic Outputs
40
90
ns
80
160
ns
5
pF
5
pF
Note 1: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > VCC) the absolute value of current at that pin should be limited to 25mA
or less.
Note 2: 0°C to 70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
correlation with worst-case test conditions.
Note 3: Typicals are parametric norm at 25°C.
Note 4: Parameter guaranteed and 100% production tested.
Note 5: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Note 6: Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.
Note 7: Cannot be tested for ML2282.
Note 8:
For VIN³ VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for
analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level
analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50mV forward bias of either diode. This means that as long as the analog VIN or VREF does not exceed the supply voltage by more than 50mV, the output code will be
correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950VDC over temperature variations, initial
tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the
minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.
Note 11: Because of multiplexer addressing, test conditions for the ML2282 would be VIN = 34kHz, 5V sine (fSAMPLING » 102kHz); ML2284 VIN = 32kHz, 5V sine
(fSAMPLING » 95kHz); ML2288 VIN = 30kHz, 5V sine (fSAMPLING » 89kHz).
Note 12: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for
comparator response time.
6
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