ML2288CIP View Datasheet(PDF) -

ML2281, ML2282, ML2284, ML2288

SINGLE-ENDED MUX MODE

MUX ADDRESS

SGL/DIF ODD/SIGN

1

0

1

1

CHANNEL#

0

1

+

+

DIFFERENTIAL MUX MODE

MUX ADDRESS

SGL/DIF ODD/SIGN

CHANNEL#

0

1

0

0

+

–

0

1

–

+

Table 3. ML2282 MUX Addressing 2 Single-Ended

or 1 Differential Channel

8 Single-Ended

0+

1+

2+

3+

4+

5+

6+

7+

COM (–)

8 Pseudo-Differential

0

+

1

+

2

+

3

+

4

+

5

+

6

+

7

+

VBIAS

COM (–)

+

4 Differential

+ (–)

0, 1

– (+)

+ (–)

2, 3

– (+)

+ (–)

4, 5

– (+)

+ (–)

6, 7

– (+)

Mixed Mode

0, 1

2, 3

4

5

6

7

VBIAS

+

–

–

+

+

+

+

+

COM (–)

+

Figure 7. Analog Input Multiplexer Functional

Options for ML2288

DIGITAL INTERFACE

The block diagram and timing diagrams in Figures 2-5

illustrate how a conversion sequence is performed.

A conversion is initiated when CS is pulsed low. This line

must me held low for the entire conversion. The converter is

now waiting for a start bit and its MUX assignment word.

A clock is applied to the CLK input. On each rising edge

of the clock, the data on DI is clocked into the MUX

address shift register. The start bit is the first logic “1” that

appears on the DI input (all leading edge zeros are

ignored). After the start bit, the device clocks in the next 2

to 4 bits for the MUX assignment word.

When the start bit has been shifted into the start location

of the MUX register, the input channel has been assigned

and a conversion is about to begin. An interval of 1/2

clock period is used for sample & hold settling through the

selected MUX channels. The SAR status output goes high

at this time to signal that a conversion is now in progress

and the DI input is ignored.

The DO output comes out of High impedance and

provides a leading zero for this one clock period.

When the conversion begins, the output of the

comparator, which indicates whether the analog input is

greater than or less than each successive voltage from the

internal DAC, appears at the DO output on each falling

edge of the clock. This data is the result of the conversion

being shifted out (with MSB coming first) and can be read

by external logic or µP immediately.

After 8 clock periods, the conversion is completed. The SAR

status line returns low to indicate this 1/2 clock cycle later.

The serial data is always shifted out MSB first during the

conversion. After the conversion has been completed, the

data can be shifted out a second time with LSB first,

depending on level of SE input. For the case of ML2288, if

SE = 1, the data is shifted out MSB first during the

conversion only. If SE is brought low before the end of

conversion (which is signalled by the high to low transition

of SARS), the data is shifted out again immediately after the

end of conversion; this time LSB first. If SE is brought low

after end of conversion, the LSB first data is shifted out on

falling edges of clock after SE goes low. For ML2282 and

2284, SE is internally tied low, so data is shifted out MSB

first, then shifted out a second time LSB first at end of

conversion. For ML2281, SE is internally tied high, so data is

shifted out only once MSB first.

All internal registers are cleared when the CS input is

high. If another conversion is desired, CS must make a

high to low transition followed by address information.

The DI input and DO output can be tied together and

controlled through a bidirectional µP I/O bit with one

connection. This is possible because the DI input is only

latched in during the MUX addressing interval while the

DO output is still in the high impedance state.

13

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