IS42S16128 View Datasheet(PDF) - Integrated Silicon Solution

Part Name

Description

Manufacturer

IS42S16128

128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM

Integrated Silicon Solution 

IS42S16128

Interval Between Read Command

A new command can be executed while a read cycle is in

progress, i.e., before that cycle completes. When the

second read command is executed, after the CAS latency

has elapsed, data corresponding to the new read com-

mand is output in place of the data due to the previous

read command.

ISSI ®

The interval between two read command (tCCD) must be

at least one clock cycle.

The selected bank must be set to the active state before

executing this command.

CLK

COMMAND READ A0 READ B0

I/O

DOUT A0 DOUT B0

tCCD

READ (CA=A, BANK 0) READ (CA=B, BANK 0)

CAS latency = 2, burst length = 4

DOUT B1

DOUT B2

DOUT B3

Interval Between Write Command

A new command can be executed while a write cycle is in

progress, i.e., before that cycle completes. At the point the

second write command is executed, data corresponding

to the new write command can be input in place of the data

for the previous write command.

The interval between two write commands (tCCD) must be

at least one clock cycle.

The selected bank must be set to the active state before

executing this command.

CLK

COMMAND

tCCD

WRITE A0 WRITE B0

I/O DIN A0 DIN B0 DIN B1 DIN B2 DIN B3

WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)

CAS latency = 2, burst length = 4

Integrated Silicon Solution, Inc. — 1-800-379-4774

25

Rev. A

03/13/00

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