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LC72723 View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
Manufacturer
LC72723
SANYO
SANYO -> Panasonic SANYO
LC72723 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
RDCL/RDDA Output Timing
• Master mode
LC72723, LC72723M
RST Operation
• Master mode
RDCL Control in Slave Mode
Caution: After an RST input, the
RDCL and RDDA outputs
stop at the high level until
the first RDS ID detection.
Parameter
RDCL setup time
RDCL high-level time
RDCL low-level time
Data output time
READY output time
Ready low-level time
Symbol
Conditions
tCS RDCL, RDDA
tCH RDCL
tCL
RDCL
tDC RDCL, RDDA
tRC RDCL, READY
tRL
READY
min
0
0.75
0.75
Ratings
typ
Unit
max
µs
µs
µs
0.75
µs
0.75
µs
107 ms
Notes:1. Start RDCL clock input after the READY signal goes low. Applications must stand by with RDCL held low when the READY pin is high.
2. Each time the RDCL input is switched from low to high to low, the application must check the READY signal level after the period tRC has elapsed
once RDCL has been set low. If READY is at the low level, the application may apply the next RDCL clock cycle. If READY is high, the application
must stop RDCL input at that point.
3. When the above timing conditions are met, RDDA can be read at either the rise or fall of the RDCL signal.
4. After the last data from memory has been read, READY will be high once the period tRC has elapsed after the fall of the RDCL signal. If even 1 bit
of data has been written to memory, READY will be low and the application will be able to read that data.
No. 6037-6/8
 

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