LC72723 View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC72723 Datasheet PDF : 8 Pages
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LC72723, LC72723M
Electrical Characteristics at Ta = –40 to +85°C, Vssd = Vssa = 0 V, Vddd = Vdda
Parameter
Input resistance
Internal feedback resistance
Center frequency
–3dB bandwidth
Gain
Stop band attenuation
Reference voltage output
Hysteresis
Low-level output voltage
High-level output voltage
High-level input current
Low-level input current
Output off leakage current
Current drain
Symbol
Conditions
Rmpxin MPXIN-Vssa: f = 57 KHz
Rcin CIN-Vssa: f = 57 KHz
Rf XIN
fc
FLOUT
BW–3dB FLOUT
Gain MPXIN-FLOUT: f = 57 KHz
Att1 FLOUT: ∆f = ±7 KHz
Att2 FLOUT: f < 45 KHz, f > 70 KHz
Att3 FLOUT: f < 20 KHz
Vref Vref: Vdda = 5 V
VHIS
VOL1
VOL2
VOH
IIH1
IIH2
IIL1
IIL2
IOFF
Idd
TEST, MODE, RST, RDCL
RDDA, RDCL : I = 2 mA
RDS-ID (READY): I = 8 mA
RDDA, RDCL : I = 2 mA
TEST, MODE, RST, RDCL : VI = 6.5 V
XIN: VI = Vddd
TEST, MODE, RST, RDCL : VI = 0 V
XIN: VI = 0 V
RDS-ID (READY): VO = 6.5 V
Vddd + Vdda
Ratings
min
typ
23
100
1.0
56.5
57.0
2.5
3.0
28
31
30
40
50
2.5
0.1 Vddd
Vddd – 0.4
2.0
2.0
8
Unit
max
KΩ
KΩ
MΩ
57.5 KHz
3.5 KHz
34
dB
dB
dB
dB
V
V
0.4
V
0.4
V
V
5.0
µA
11
µA
5.0
µA
11
µA
5.0
µA
mA
Inputs and Outputs
TEST
0
0
1
1
MODE
0
1
0
1
Circuit operating mode
Master mode
Slave mode
Standby mode (crystal oscillator stopped)
IC test mode (Cannot be set by users.)
RDCL pin
Clock output
Clock input
—
—
RDS-ID/READY pin
RDS-ID output
READY output
—
—
RST = 0
RST = 1
RST pin
Normal operation
The RDS-ID and demodulation circuits are cleared, and (in slave mode) the READY state and memory are cleared.
Master mode RDS-ID output (active low)
Slave mode Readout data ready output (active low)
RDS ID/READY pin
Note: The RDS-ID (READY) pin is an n-channel open-drain output, and data is read out by connecting a pull-up resistor.
No. 6037-5/8
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