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M38861F9A-XXXHP View Datasheet(PDF) - MITSUBISHI ELECTRIC

Part NameDescriptionManufacturer
M38861F9A-XXXHP RAM size 2048bytes; single-chip 8-bit CMOS microcomputer Mitsubishi
MITSUBISHI ELECTRIC  Mitsubishi
M38861F9A-XXXHP Datasheet PDF : 110 Pages
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MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 Interrupt vector addresses and priority
Interrupt Source
Reset (Note 2)
Priority
1
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
INT0
2
Input buffer full
(IBF)
FFFB16
FFFA16
INT1
Output buffer
empty (OBE)
3
FFF916
FFF816
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
Remarks
Non-maskable
External interrupt
(active edge selectable)
At input data bus buffer writing
At detection of either rising or External interrupt
falling edge of INT1 input
(active edge selectable)
At output data bus buffer read-
ing
Serial I/O1
reception
4
Serial I/O1
transmission
5
SCL, SDA
Timer X
6
Timer Y
7
Timer 1
8
Timer 2
9
CNTR0
10
SCL, SDA
CNTR1
11
Key-on wake-up
Serial I/O2
12
I2C
INT2
13
I2C
INT3
14
INT4
15
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
At detection of either rising or
falling edge of SCL or SDA
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of SCL or SDA
At detection of either rising or
falling edge of CNTR1 input
At falling of port P3 (at input) in-
put logical level AND
At completion of serial I/O2 data
transfer
At completion of data transfer
At detection of either rising or
falling edge of INT2 input
At completion of data transfer
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling valid)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
A-D converter
16
Key-on wake-up
FFDF16
FFDE16
At completion of A-D conversion
At falling of port P3 (at input) in-
put logical level AND
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
External interrupt (falling valid)
Non-maskable software interrupt
20
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