AD1843JS View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD1843JS Datasheet PDF : 64 Pages
| |||
AD1843
interval to update the DAC Not Full status bits. Therefore
driver software does not have to make provision for frame-to-
frame delays between control and status information; the infor-
mation in each frame is always up to date.
The AD1843 supports locking to an external clock which may
result in a sample rate that is marginally higher than the nominal
audio standard maximum sample rate of 48 kHz. This is neces-
sary since two crystal-based clock sources are never perfectly
matched to one another. One is always at a slightly higher fre-
quency. The AD1843 conversion channels have been designed
to support sample rates that are up to 2.1% higher than 48 kHz
(i.e., 49 kHz), referenced to the AD1843’s clock input on
XTALI, when all conversion channels are simultaneously run-
ning. Even higher rates can be supported when all channels are
not running simultaneously. See the “Conversion Rates” sec-
tion above for additional details. The serial interface must also
allow for this higher sample rate with a frame sync (SDFS) rate
that is at least as high as the sample rate in 16 slot per frame
mode, or half as high as the sample rate in 32 slot per frame
mode. When the AD1843 is bus master, the SCLK frequency
is either 12.288 MHz or 16.384 MHz, which allows for up to
48 kHz or 64 kHz sampling rates, respectively.
The AD1843 Control Registers are read and written by trans-
mitting a read/write request bit along with the Control Register
address in the slot 0 Control Word. When a read is requested,
the contents of the Control Register addressed is transmitted
out during slot 1 of the following frame. When a write is re-
quested, data to be written must be transmitted to the AD1843
in slot 1, and the former contents of the control register are
transmitted out during slot 1 of the following frame. Unless oth-
erwise noted, Control Register writes do not take effect until the
current round of six communication TDM time slots concludes.
Equivalently, unless otherwise noted, Control Register writes do
not take effect until the subsequent falling edge of the TSO signal.
The following sections describe the bit assignments for all time
slots.
SCLK
TIME
SLOT 0
TIME
SLOT 1
TIME
SLOT 2
TIME
SLOT 3
TIME
SLOT 4
TIME
SLOT 5
SDFS
16 BITS
SDI
16-BIT
STEREO SDO
IGNORED
3-STATED
CONTROL WORD REGISTER DATA
STATUS WORD REGISTER DATA
DAC1 LEFT
ADC LEFT
DAC1 RIGHT
ADC RIGHT
DAC2 LEFT
0s
DAC2 RIGHT
0s
IGNORED
3-STATED
16-BIT
SDI
MONO
DAC1, DAC2
SDO
SDI
8-BIT
STEREO SDO
IGNORED
3-STATED
IGNORED
3-STATED
CONTROL WORD REGISTER DATA
STATUS WORD REGISTER DATA
DAC1
ADC LEFT
DON'T CARE
ADC RIGHT
DAC2
0s
DON'T CARE
0s
IGNORED
3-STATED
CONTROL WORD REGISTER DATA
STATUS WORD REGISTER DATA
DAC1L
ADCL
DON'T
CARE
0s
DAC1R
ADCR
DON'T
CARE
0s
DAC2L
DON'T
CARE
0s
DAC2R
DON'T
CARE
0s
IGNORED
3-STATED
8-BIT
SDI
MONO
DAC1, DAC2 SDO
IGNORED
3-STATED
CONTROL WORD REGISTER DATA
STATUS WORD REGISTER DATA
DAC1
ADCL
DON'T
CARE
0s
DON'T CARE
ADCR 0s
DAC2
DON'T
CARE
0s
DON'T CARE
0s
IGNORED
3-STATED
THE DIAGRAM ABOVE IS INTENDED TO BE ILLUSTRATIVE OF THE MORE COMMONLY USED CONFIGURATIONS. ADC LEFT, ADC RIGHT, DAC1
AND DAC2 CAN BE INDIVIDUALLY ASSIGNED TO 8-BIT OR 16-BIT SAMPLE WIDTH, AND DAC1 AND DAC2 CAN BE INDIVIDUALLY ASSIGNED
TO STEREO OR MONO MODE. EACH AD1843 CONSUMES 6 TMD SLOTS (REQUIRING 96 SCLK PERIODS), LEAVING 10 TDM SLOTS
UNUSED IN A 16 SLOT FRAME.
NOTE THAT BECAUSE THE SERIAL INTERFACE AND THE ADC AND DACS ARE IN GENERAL ASYNCHRONOUS, NOT EVERY CAPTURE OR
PLAYBACK TIME SLOT WILL CONTAIN VALID DATA. THE HOST PROCESSOR MUST POLL THE STATUS WORD TO DETERMINE WHETHER
THE ADC DATA IS VALID AND WHETHER THE DAC IS REQUESTING ADDITIONAL SAMPLES.
Figure 11. AD1843 Slot Assignments
REV. 0
–21–
|
|
Share Link: 