AD1843JS View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD1843JS

Serial-Port 16-Bit SoundComm Codec

Analog Devices 

AD1843

Modem Data Access Arrangement (DAA) devices are generally

differential on the transmit side, and single-ended on the receive

side. The DAA transmit input (generally differential) should be

connected to the DAC2 output, pins LOUT2LP and LOUT2LN,

or LOUT2RP and LOUT2RN. The DAA receive output

(generally single-ended) should be connected to one of the

ADC line inputs, LINLP or LINRP. See the “APPLICATION

CIRCUITS” section below for more detail on the electrical

connections. There are several software driver steps that are re-

quired to configure the SoundComm codec for use as a modem

AFE.

Configure DAC2

1. Set the DA2FLT bit (Control Register Address 25, Bit 9) to

“1,” to select the digital modem filter mode. The DAC2 out-

puts can be used either as differential outputs or single-ended

outputs depending on how the pins are connected electrically;

no Control Register writes are required to configure the DAC2

outputs as either differential or single-ended.

2. Program LDA2G5:0 (Control Register Address 10, Bits 8

through 13) to “00 0101” (i.e., +4.5 dB) or RDA2G5:0

(Control Register 10, Bits 0 through 5) to “00 0101” (i.e.,

+4.5 dB), depending on whether the DAA transmit input is

connected to the left channel DAC2 output (use LDA2G5:0)

or the right channel DAC2 output (use RDA2G5:0). This

code establishes the DAC2 nominal analog output swing at

3.156 V p-p single-ended, or 6.312 V p-p differentially. The

3.156 V p-p level is equivalent to 3.17 dBm.

Configure ADC

1. Set the ADLFLT bit (Control Register Address 25, Bit 0) to

“1,” or the ADRFLT bit (Control Register Address 25, Bit 1)

to “1,” to select the digital modem filter mode. Set ADLFLT

if the DAA receive output is connected to the AD1843

LINLP input; set ADRFLT if the DAA receive output is

connected to the AD1843 LINRP input. Set the LINLSD bit

(Control Register Address 28, Bit 0) to “1” if the DAA is

connected to the AD1843 LINLP input; set the LINRSD bit

(Control Register Address 28, Bit 1) to “1” if the DAA is

connected to the AD1843 LINRP input.

2. Program LIG3:0 (Control Register Address 2, Bits 8 through

11) to “0000” (i.e., 0.0 dB) or RIG3:0 (Control Register

Address 2, Bits 0 through 3) to “0000” (i.e., 0.0 dB) de-

pending on whether the left or right ADC input channel is

being used for the modem function. This code maps an ana-

log input swing of 3.156 V p-p to the full dynamic range of

the 16-bit digital sample (i.e., ± 215). The 3.156 V p-p level is

equivalent to 3.17 dBm.

Note that if the AD1843 is to be reconfigured dynamically, the

affected converter must be powered down before its associated

digital filter can be changed. In other words, if the digital filter

for the ADC left channel is being changed from audio mode to

modem mode, the ADC left channel must be powered down

first (using the ADLEN bit in Control Register Address 27).

Use the ADREN bit in Control Register Address 27 for the

ADC right channel, the DAC1EN bit in Control Register

Address 27 for DAC1, and the DAC2EN bit in Control Regis-

ter Address 27 for DAC2.

Typical Configurations

Figure 6 below illustrates example connections between the

AD1843 SoundComm codec and other system resources. The

rich analog input and output connectivity of the AD1843 allows

a wide variety of configuration possibilities. Note that the level

of modem, speakerphone and external speaker concurrency is

application and DSP resource dependent.

SERIAL INTERFACE

The AD1843 SoundComm Codec transmits and receives both

data and control/status information through its serial port.

The AD1843 can be configured as either master or slave of the

serial interface. This is selected by using the BM pin. When

BM is tied HI, the AD1843 serves as bus master and supplies

the frame sync and the serial clock. When BM is tied LO, the

AD1843 serves as bus slave and receives the frame sync and the

serial clock. The level on BM should not be altered unless the

reset pin (RESET) is asserted.

The AD1843 has six pins devoted to the serial interface: SDI,

SDO, SCLK, SDFS, TSI and TSO. The SDI pin is for serial

data input to the AD1843 and the SDO pin is for serial data

output from the AD1843. The SCLK pin is the serial interface

clock. Communication in and out of the AD1843 requires bits

of data to be transmitted after a rising edge of SCLK, and

sampled on a falling edge of SCLK. When the AD1843 is bus

master (BM pin tied HI), the SCLK frequency driven by the

AD1843 will be 12.288 MHz by default, but this can be in-

creased to 16.384 MHz by setting the SCF bit in Control Regis-

ter 26. When the AD1843 is bus slave (BM pin tied LO), the

SCLK frequency driven to the AD1843 may be as high as

24.576 MHz, but must not be any higher than the frequency on

the XTALI pin.

The SDFS pin is for the serial interface frame sync. When bus

master, new frames are marked by a HI pulse driven out on

SDFS one serial clock period before the frame begins. When

bus slave, new frames must be marked by a LO to HI transition

driven in on SDFS one serial clock period before the frame be-

gins, but the transition back from HI to LO may occur at any

time provided the HI and LO times of SDFS are at least one

SCLK period in duration each.

When the AD1843 is bus master, frame size is controlled by the

FRS bit in Control Register 26. When FRS is set to “1,” each

frame is divided into 16 slots of 16 bits. When FRS is reset to

“0,” each frame is divided into 32 slots of 16 bits. In 32 slot

configuration, the second 16 slots of a frame must have slot as-

signments that are identical to the first 16 slots of the frame; 32

slot configuration is essentially 16 slot configuration with every

other SDFS pulse missing. Although these are the frame sizes

REV. 0

–19–

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