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ADV7182 View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
ADV7182 Datasheet PDF : 96 Pages
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Data Sheet
ADV7182
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.71 V to 3.46 V, specified at operating temperature
range, unless otherwise noted.
Table 4.
Parameter
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I2C PORT
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Times
SCLK and SDATA Fall Times
Setup Time for Stop Condition
RESET FEATURE
RESET Pulse Width
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
Symbol Test Conditions/Comments
Min Typ
Max Unit
28.63636
MHz
±50 ppm
400 kHz
t1
0.6
μs
t2
1.3
μs
t3
0.6
μs
t4
0.6
μs
t5
100
ns
t6
300 ns
t7
300 ns
t8
0.6
μs
5
ms
t9:t10
45:55
55:45 % duty cycle
t11
Negative clock edge to start of valid data
(tACCESS = t10 − t11)
t12
End of valid data to negative clock edge
(tHOLD = t9 + t12)
3.8 ns
6.9 ns
Timing Diagrams
t3
t5
t3
SDATA
SCLK
t6
t1
t2
t7
t4
t8
Figure 2. I2C Timing
OUTPUT LLC
t9
t10
OUTPUTS P0 TO P7, HS,
VS/FIELD/SFL
t12
t11
Figure 3. Pixel Port and Control Output Timing
Rev. A | Page 7 of 96
 

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