ADV7182WBCPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV7182WBCPZ-RL Datasheet PDF : 96 Pages
| |||
ADV7182
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
DGND 1
DVDDIO 2
DVDD 3
DGND 4
P7 5
P6 6
P5 7
P4 8
ADV7182
TOP VIEW
(Not to Scale)
24 INTRQ
23 AIN4
22 AIN3
21 AVDD
20 VREFN
19 VREFP
18 AIN2
17 AIN1
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Type
1, 4
DGND
G
2
DVDDIO
P
3, 13
DVDD
P
5 to 12
P7 to P0
O
14
XTALP
O
15
XTALN
I
16
PVDD
P
Description
Ground for Digital Supply.
Digital I/O Supply Voltage (1.8 V to 3.3 V).
Digital Supply Voltage (1.8 V).
Video Pixel Output Port.
This pin should be connected to the 28.6363 MHz crystal or not connected if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7182. In crystal mode, the
crystal must be a fundamental crystal.
Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,
28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
PLL Supply Voltage (1.8 V).
17, 18, 22, 23
19
20
21
24
25
AIN1 to AIN4
VREFP
VREFN
AVDD
INTRQ
RESET
26
ALSB
27
SDATA
28
SCLK
I
Analog Video Input Channels.
O
Internal Voltage Reference Output.
O
Internal Voltage Reference Output.
P
Analog Supply Voltage (1.8 V).
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video.
I
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7182 circuitry.
I
This pin selects the I2C address for the ADV7182. For ALSB set to Logic 0, the address
selected for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.
I/O I2C Port Serial Data Input/Output Pin.
I
I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
29
VS/FIELD/SFL
O
Vertical Synchronization Output Signal/Field Synchronization Output Signal/Subcarrier
Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier
frequency when this decoder is connected to any Analog Devices digital video encoder.
30
HS
O
Horizontal Synchronization Output Signal.
31
PWRDWN
I
A logic low on this pin places the ADV7182 is in power-down mode.
32
LLC
O
Line-Locked Output Clock for Output Pixel Data. Nominally 27 MHz but varies up or down
according to the video line length.
EPAD (EP)
The exposed pad must be connected to DGND.
Rev. A | Page 10 of 96
|
|
Share Link: 