ADM8697AN(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADM8697AN Datasheet PDF : 12 Pages
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ADM8696/ADM8697
TYPICAL APPLICATIONS
ADM8696
Figure 18 shows the ADM8696 in a typical power monitoring,
battery backup application. VOUT powers the CMOS RAM.
Under normal operating conditions with VCC present, VOUT is
internally connected to VCC. If a power failure occurs, VCC will
decay and VOUT will be switched to VBATT, thereby maintaining
power for the CMOS RAM.
Power Fail RESET
The VCC power supply is also monitored by the Low Line In-
put, LLIN. A RESET pulse is generated when LLIN falls below
1.3 V. RESET will remain low for 50 ms after LLIN returns
above 1.3 V. This allows for a power-on reset and prevents re-
peated toggling of RESET if the VCC power supply is unstable.
Resistors R3 and R4 should be chosen to give the desired VCC
reset threshold.
Watchdog Timer
The Watchdog Timer Input (WDI) monitors an I/O line from
the µP system. This line must be toggled once every 1.6 s to
verify correct software execution. Failure to toggle the line indi-
cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
If the watchdog timer is not needed the WDI input should be
left floating.
Power Fail Detector
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network R1 and R2. This input is intended as
an early warning power fail input. The voltage on the PFI input
is compared with a precision 1.3 V internal reference. If the in-
put voltage drops below 1.3 V, a power fail output (PFO) signal
is generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold volt-
age VT. The threshold should be set at a higher voltage than the
RESET threshold so there is sufficient time available to com-
plete the shutdown procedure before the processor is RESET
and power is lost.
+5V
RESET
R3
R1
VCC
PFI
VOUT
LLIN
R4 R2 ADM8696
RESET
+
BATTERY
VBATT
PFO
WDI
GND
µP POWER
CMOS RAM
POWER
µP SYSTEM
µP RESET
µP NMI
I/O LINE
Figure 18b shows a similar application for the ADM8696 but in
this case the PFI input monitors the unregulated input to the
7805 voltage regulator. This gives an earlier warning of an im-
pending power failure. It is useful with processors operating at
low speeds or where there are a significant number of house-
keeping tasks to be completed before the power is lost.
INPUT
POWER
R1
R2
7805
0.1µF
0.1µF
3V
BATTERY
VCC
VBATT
BATT VOUT
ON
ADM8696
PFI
GND
WDI
R3
OSC IN
NC
PFO
OSC SEL
RESET
LLIN
R4
RESET LOW LINE WDO
VCC
CMOS RAM
A0–A15 µP
POWER
I/O LINE
NMI
µP
RESET
SYSTEM STATUS
INDICATORS
Figure 18b. ADM8696 Typical Application Circuit B
This application also shows an optional external transistor that
may be used to provide in excess of 100 mA current on VOUT.
When VCC is higher than VBATT, the BATT ON output goes
low, providing 25 mA of base drive for the external PNP transis-
tor. The maximum current available is dependent on the power
rating of the external transistor.
RAM Write Protection
The ADM8697 CEOUT line drives the Chip Select inputs of the
CMOS RAM. CEOUT follows CEIN as long as LLIN is above the
reset threshold. If LLIN falls below the reset threshold, CEOUT
goes high, independent of the logic level at CEIN. This prevents
the microprocessor from writing erroneous data into RAM dur-
ing power-up, power-down, brownouts and momentary power
interruptions.
Figure 18a. ADM8696 Typical Application Circuit A
–10–
REV. 0
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