ZPSD301-B-15J View Datasheet(PDF) - Waferscale Integration

Part Name

Description

Manufacturer

ZPSD301-B-15J

Programmable system device, 18 PLD inputs, EPROM 512K, bus width x8 or x16, 5V, 90ns

Waferscale Integration 

PSD3XX Family

10.

I/O Port

Functions

(cont.)

10.3 Port B (PB0-PB7)

The control registers of Port B are located in CSIOPORT space; see Table 5A and 5B.

10.3.1 Port B (PB0-PB7) in Multiplexed Address/Data Mode

Each pin of Port B can be individually configured. The following table summarizes what the

control registers (in CSIOPORT space) for Port B do:

Register Name

0 Value

Port B Pin Register

Port B Direction Register

Port B Data Register

Sampled logic level

at pin = ‘0’

Pin is configured

as input

Data in DFF = ‘0’

NOTE: 1. Default value is the value after reset.

1 Value

Sampled logic level

at pin = ‘1’

Pin is configured

as output

Data in DFF = ‘1’

Default

Value

(Note 1)

X

0

0

MCU I/O Mode

The default configuration of Port B is MCU I/O. In this mode, every pin can be set

(at run-time) as an input or output by writing to the respective pin’s direction flip-flop (DIR

FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin’s

data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the

pin. The contents of the Pin Register indicate the true state of the PSD driving the pin

through the DFF or an external source driving the pin. Pins can be configured as CMOS

or open-drain using WSI’s PSDsoft software. Open-drain pins require external pull-up

resistors.

Chip Select Output

Alternatively, each bit of Port B can be configured to provide a chip-select output signal

from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins is

not limited to chip selects only; they can be used for generic combinatorial logic as well.

Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7

signals is comprised of two product terms.

18

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