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T7570 View Datasheet(PDF) - Agere -> LSI Corporation

Part Name
Description
Manufacturer
T7570 Datasheet PDF : 28 Pages
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T7570 Programmable PCM Codec
with Hybrid-Balance Filter
Data Sheet
October 1996
Functional Description (continued)
Transmit Filter and Encoder (continued)
converter has a compressing characteristic according
to the standard ITU-T A- or µ-coding laws selected by a
control instruction (see Tables 2 and 3). A precision on-
chip voltage reference helps ensure accurate and
highly stable transmission levels. Any offset voltage
arising in the gain-set amplifier, the filters, or the com-
parator is canceled by an internal autozero circuit.
Decoder and Receive Filter
PCM data is shifted into the decoder's receive PCM
register via the DR0 or DR1 pin during the selected time
slot on eight falling edges of BCLK. The decoder con-
sists of an expanding digital-to-analog convertor with
either A- or µ-law decoding characteristic, which is
selected by the same control instruction used to select
the encode law. Following the decoder is a fifth-order,
low-pass, switched-capacitor filter with Sin(x)/x correc-
tion for the 8 kHz sample and hold. A programmable
gain amplifier that is set by writing to the receive gain
register is included, followed by a power amplifier capa-
ble of driving a 300 load to 4.0 V peak to peak.
PCM Interface
The FSX and FSR frame-sync inputs determine the
beginning of the 8-bit transmit and receive time slots,
respectively. They can have any duration from a single
cycle of BCLK high to one MCLK period low. Two differ-
ent relationships can be established between the
frame-sync inputs and the actual time slots on the PCM
buses by setting bit 3 in the control register (see
Table 3). Nondelayed data mode is similar to long-
frame timing of other codecs for which time slots begin
nominally coincident with the rising edge of the appro-
priate FS input. The alternative is to use delayed-data
mode in which each FS input must be high at least a
half-cycle of BCLK earlier than the time slot. The time-
slot assignment circuit on the device can only be used
with delayed-data timing.
The time-slot assignment capability of this device is a
subset of the Lucent concentration highway interface.
The beginning of the first time slot in a frame is identi-
fied by the appropriate FS input. The actual transmit
and receive time slots are then determined by the inter-
nal time-slot assignment counters.
Transmit and receive frames and time slots can be
skewed from each other by any number of BCLK cycles
by offsetting FSR and FSX. During each assigned trans-
6
mit time slot, the selected DX0/1 output shifts data out
from the PCM register on the rising edges of BCLK.
TS X0 (or TS X1 as appropriate) also pulls low for the
first 7.5 bit times of the time slot to control the high-
impedance state enable of a backplane line driver.
Serial PCM data is shifted into the selected DR0/1 input
during each assigned receive time slot on the falling
edges of BCLK. DX0 or DX1 and DR0 or DR1 are select-
able on the T7570 (see the Port Selection section
under Programmable Functions).
Serial Control Port
Programmable register instructions (Table 2) are writ-
ten into or read back from the T7570 via the serial con-
trol port consisting of the control clock (CCLK), the
serial data input (CI) and output (CO), and the chip-
select input (CS ) (see Figure 6). All instructions
require 2 bytes, with the exception of a single-byte
powerup/powerdown command. The bits in byte 1 are
defined as follows: bit 7 specifies powerup or power-
down; bits 6, 5, 4, and 3 specify the register address;
bit 2 specifies whether the instruction is a read or a
write; bit 1 specifies a one- or two-byte instruction; and
bit 0 is not used.
To shift control data into the T7570, CCLK must be
pulsed high eight times while CS is low. Data on the CI
input is shifted into the serial input register on the fall-
ing edge of each CCLK pulse. After all data is shifted
in, the contents of the input shift register are decoded
and can indicate that a second byte of control data
follows. This second byte can either be defined by a
second byte wide CS pulse or can follow the first con-
tiguously; it is not mandatory for CS to return high
between the first and second control bytes.
At the end of the eighth CCLK pulse in the second con-
trol byte, the data is loaded into the appropriate pro-
grammable register. CS can remain low continuously
when programming successive registers, if desired.
However, CS should be set high when no data trans-
fers are in progress.
To read back interface latch data or status information
from the T7570, the first byte of the appropriate instruc-
tion, as defined in Table 2, is strobed in during the first
CS pulse. CS must then be taken low for a further
eight CCLK cycles, during which the data is shifted
onto the CO pin on the rising edges of CCLK. When
CS is high, the CO pin is in the high-impedance state,
enabling the CO pins of many devices to be multiplexed
together.
Lucent Technologies Inc.
 

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