T7570 View Datasheet(PDF) - Agere -> LSI Corporation
Part Name
Description
Manufacturer
T7570 Datasheet PDF : 28 Pages
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T7570 Programmable PCM Codec
with Hybrid-Balance Filter
Data Sheet
October 1996
Pin Information (continued)
Table 1. Pin Description
Pin Symbol Type
Name/Description
1
GND
— Ground. All analog and digital signals are referenced to this pin.
2 VFRO O Receive Analog Power Amplifier Output. This pin can drive load impedances as low
as 300 Ω. PCM data received on the assigned DR pin is decoded and appears at this
output as a voice-frequency signal.
3
NC
— No Connect. Connections may be made to or traces may be routed through this pin.
4
NC
— No Connects. Do not make connections to or route traces through pins 4 and 5.
5
6
IL3
I/O Interface Latch I/O. These pins can be individually programmed as inputs or outputs
7
IL2
I/O as determined by the state of the corresponding bits in the latch direction register
(LDR). For pins configured as inputs, the logic state sensed on each input is latched
into the interface latch register (ILR) whenever control data is written to the T7570, and
the information is shifted out on the CO pin. When configured as outputs, control data
written into the ILR appears at the corresponding IL pins.
8
FSR
I Receive Frame-Sync Input. A pulse or square-wave waveform with an 8 kHz repeti-
tion rate is applied to this input to define the start of the receive time slot assigned to
this device (nondelayed frame mode), or the start of the receive frame (delayed frame
mode using the internal time-slot assignment counter).
9
DR1
10
DR0
I Receive PCM Inputs. These receive data input(s) are inactive except during the
I assigned receive time slot of the assigned port when the receive PCM data is shifted in
on the falling edges of BCLK.
11
CO
O Control Output. Serial control information is shifted out from the T7570 on this pin
when CS is low. It can be connected to CI if required.
12
CI
I Control Input. Serial control information is shifted into the T7570 on this pin when CS
is low. It can be connected to CO if required.
13 CCLK
I Control Clock. This clock shifts serial control information into CI or out from CO when
the CS is low, depending on the current instruction. CCLK can be asynchronous with
the other system clocks.
14
CS
I Chip Select (Active-Low). When this pin is low, control information can be written into
or read from the T7570 via the CI and CO pins.
15
MR
I Master Reset. This logic input must be pulled low for normal operation of the T7570.
When pulled momentarily high (at least 1 µs), all programmable registers in the device
are reset to the states specified under powerup initialization.
16 BCLK
I Bit Clock Input. This pin shifts PCM data into and out of the DR and DX pins. BCLK
can vary from 64 kHz to 4.096 MHz in 8 kHz increments and must be synchronous with
MCLK at the start of each frame. MCLK can be used as BCLK.
17 MCLK
I Master Clock. The master-clock input is used by the switched capacitor filters and the
encoder and decoder sequencing logic. It must be 1.536 MHz, 1.544 MHz,
2.048 MHz, or 4.096 MHz and must be synchronous with BCLK at the start of each
frame.
18
DX0
19
DX1
O Transmit PCM Output. These transmit-data, high-impedance state outputs remain in
O the high-impedance state except during the assigned transmit time slot on the
assigned port, during which the transmit PCM data byte is shifted out on the rising
edges of BCLK.
20 TS X0
21 TS X1
O Backplane Line Driver Enable (Active-Low). Normally, these open-drain outputs are
O floating in a high-impedance state. When a time slot is active on one of the DX outputs,
the appropriate TS X output pulls low to enable a backplane line driver.
4
Lucent Technologies Inc.
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