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ADC180CA View Datasheet(PDF) - Thaler Corporation

Part Name
Description
Manufacturer
ADC180CA
Thaler
Thaler Corporation Thaler
ADC180CA Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
CONNECTING THE ADC180
DUTY CYCLE OUTPUT (pin 3)
This logic level output allows monitoring of the
integration cycle and is usually used for timing
purposes.
POWER SUPPLIES (pins 4-7)
The ADC180 has internal 0.1µF decoupling
capacitors for all power supply inputs. This is
sufficient for applications with relatively short power
supply leads (approx. 5") or if additional capacitors
are located on the circuit board. External capacitors
of 10 µF on the ±15V inputs and 33 µF on the +5V
input is recommended for applications with longer
power supply leads.
GROUND (pin7)
Since ground noise can result in a loss of accuracy,
the ground connection should be made as solid as
possible. Use of a ground plane is a good approach
to maintain the full accuracy of the ADC180.
OUTPUT DATA LINES (pins 13-20)
The parallel output data is available on pins 13-20.
Pin 20 is the Most Significant Bit and pin 13 the
Least Significant Bit. The data lines go to a high
impedance state when the Output Enable line is at a
logic 1 level.
N.C. 1
N.C. 2
Duty Cycle Output 3
Vee (-15V) 4
Vcc (+15V) 5
Vdd (+5V) 6
GND
7
N.C.
8
N.C.
9
N.C.
10
N.C.
11
N.C.
12
D0
13
D1
14
D2
15
D3
16
D4
17
D5
18
D6
19
D7
20
(TOP VIEW)
ADC180
40 ANALOG LOW
39 ANALOG HIGH
38 N.C.
37 N.C.
36 N.C.
35
CAPACITOR
34
33 N.C.
32 N.C.
31 N.C.
30 N.C.
29 /AUTO ZERO / RESET
28 N.C.
27 N.C.
26 20MHz CLOCK OUTPUT
25 N.C.
24 S1
23 S0
22 /DATA REQUEST
21 /OUTPUT ENABLE
FIGURE 3. EXTERNAL CONNECTIONS
ANALOG INPUTS (pins 39,40)
The differential analog inputs are buffered by
op amps and have a common mode rejection of
approximately 80dB minimum. To maintain the full
accuracy of the ADC180 it is recommended to
maintain the input to analog low to less than
0.1VDC. To avoid differential noise pickup, parallel
adjacent lines should be used for the analog inputs
on PC boards and shielded lines outside of the PC
connections.
CAPACITOR (pin 34, 35)
The only external component required to operate
the ADC180 is a capacitor which sets the
integration time. A 0.082 µF capacitor results in an
integration time of approximately 250 µs. For 2,000
µs a 0.68µF capacitor is required. The relationship
is linear for intermediate capacitor values.
The main parameter affected by shorter conversion
times is bias stability over temperature.
Polystyrene, mylar, or polycarbonate capacitors are
recommended.
AUTO ZERO / RESET (pin 29)
A logic 0 on this input will autozero the ADC180 by
internally connecting the analog high to analog low.
Since the internal microprocessor is reset, the
ADC180 is not functional during this time
(approximately 1s). S1 will go to logic 1 indicating
that no data is available. After completing the
autozero function, S1 will return to logic 0 and the
ADC will begin collecting data.
20MHz CLOCK OUTPUT (pin 26)
Output of the internal crystal oscillator.
STATUS LINES (pins 23, 24)
These lines indicate the present state of the ADC.
After a data request has been received and the
current integration cycle is complete, the ADC will
output the data collected subsequent to the
previous data request. S1 will go to logic 1 to
acknowledge the data request. The 8 bytes of data
will be placed on the data bus sequentially. A logic
1 on S0 indicates valid data on the data bus. After
the data has been transmitted, S1 will return to
logic 0.
DATA REQUEST (pin 22)
A logic 0 on this line initiates a data transfer
sequence.
OUTPUT ENABLE (pin 21)
A logic 0 on this line enables outputs D0 - D7.
NC= Factory test points, do not connect to these pins.
ADC180DS REV H MAR 00
 

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