Q-67107-H5236 View Datasheet(PDF) - Micronas
Part Name
Description
Manufacturer
Q-67107-H5236 Datasheet PDF : 154 Pages
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SDA 9402/02S(A31)
Preliminary Data Sheet 02.2001
Features
2
Features
• Integrated Video Matrix switch
– Up to seven CVBS inputs, up to two Y/C inputs,
– Up to three CVBS outputs (even when Y/C input)
– 9 bit amplitude resolution for CVBS, Y/C A/D converter
– AGC (Automatic Gain Control)
• Multi-standard color decoder
– PAL/NTSC/SECAM including all substandards
– Automatic recognition of chroma standard
– Only one crystal necessary for all standards
• RGB-FBL or YUV-H-V input
– 8 bit amplitude resolution for RGB or YUV
– 8 bit amplitude resolution for FBL or H
• ITU656 support
– ITU656 input (9402)
– ITU656 input or output (9402S, pin sharing)
• Noise reduction
– Motion adaptive temporal noise reduction
– Field-based temporal noise reduction for luminance and chrominance
– Different motion detectors for luminance and chrominance or identical
– Flexible programming of the temporal noise reduction parameters
– Automatic measurement of the noise level
• Horizontal scaling of the 1fH signal
– Split-screen possible with additional PiP or Text processor
• Flexible digital horizontal scaling of the 2fH signal
– Scaling factors: 3, ... [2 pixel resolution], ..., 0.75 including 16:9 compatibility
– 5 zone panorama generator
• Embedded memory
– On-chip memory controller
– Embedded DRAM core for field memory
– SRAM for PAL/SECAM delay line
• Data format 4:2:2
• Flexible clock and synchronization concept
– Horizontal line-locked or free-running mode
– Vertical locked or free-running mode
• Scan-rate-conversion
– Simple interlaced modes (100/120 Hz): AABB, AAAA, BBBB (9402 only)
– No scan-rate-conversion modes (50/60 Hz): AB, AA, BB (9402S only)
• Flexible output sync controller
– Flexible positioning of the output signal
– Flexible programming of the output sync raster
– ’Blank signal’ generation
Micronas
2-9
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