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AD1674AR-REEL View Datasheet(PDF) - Analog Devices

Part Name
Description
Manufacturer
AD1674AR-REEL
ADI
Analog Devices ADI
AD1674AR-REEL Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD1674
(for all grades TMIN to TMAX with VCC = +15 V ؎ 10% or +12 V ؎ 5%,
SWITCHING SPECIFICATIONS VLOGIC = +5 V ؎10%, VEE = –15 V ؎ 10% or –12 V ؎ 5%; VIL = 0.4 V,
VIH = 2.4 V unless otherwise noted)
CONVERTER START TIMING (Figure 1)
Parameter
J, K, A, B, Grades T Grade
Symbol Min Typ Max Min Typ Max Units
Conversion Time
8-Bit Cycle
tC
12-Bit Cycle
tC
STS Delay from CE
tDSC
CE Pulse Width
tHEC
CS to CE Setup
tSSC
CS Low During CE High tHSC
R/C to CE Setup
tSRC
R/C Low During CE High tHRC
A0 to CE Setup
tSAC
A0 Valid During CE High tHAC
7
9
50
50
50
50
50
0
50
8
7 8 µs
10
9 10 µs
200
225 ns
50
ns
50
ns
50
ns
50
ns
50
ns
0
ns
50
ns
READ TIMING—FULL CONTROL MODE (Figure 2)
Parameter
J, K, A, B, Grades T Grade
Symbol Min Typ Max Min Typ Max Units
CE
tHEC
__
CS
tHSC
tSSC
_
R/C
tSRC tHRC
A0
tSAC
tHAC
tC
STS
DB11 – DB0
tDSC
HIGH IMPEDANCE
Figure 1. Converter Start Timing
Access Time
tDD1
Data Valid After CE Low tHD
Output Float Delay
tHL5
CS to CE Setup
tSSR
R/C to CE Setup
tSRR
A0 to CE Setup
tSAR
CS Valid After CE Low tHSR
R/C High After CE Low tHRR
A0 Valid After CE Low tHAR
75 150
75 150 ns
252
252
ns
203
154
ns
150
150 ns
50
50
ns
0
0
ns
50
50
ns
0
0
ns
0
0
ns
50
50
ns
NOTES
1tDD is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
20°C to TMAX.
3At –40°C.
4At –55°C.
5tHL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
Test
VCP
COUT
_C_E
CS
tSSR
tHSR
_
R/C
tSSR
tHRR
A0
tSAR
tHAR
STS
DB11 – DB0
HIGH
IMPEDANCE
tHS
tHD
DATA
VALID
tDD
tHL
Figure 2. Read Timing
Access Time High Z to Logic Low
5V
100 pF
IOL
Float Time Logic High to High Z
0V
10 pF
Access Time High Z to Logic High
0V
100 pF
Float Time Logic Low to High Z
5V
10 pF
DOUT
COUT
VCP
HIGH
IMP.
IOH
Figure 3. Load Circuit for Bus Timing Specifications
REV. C
–5–
 

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