ICS9148-25 View Datasheet(PDF) - Integrated Circuit Systems

Part Name

Description

Manufacturer

ICS9148-25

Pentium/Pro™ System and Cyrix™ Clock Chip

Integrated Circuit Systems 

ICS9148-25

Technical Pin Function Descriptions

CPU3.3_2.5#

This Input pin controls the CPU and IOAPIC output buffer

strength for skew matching CPU and SDRAM outputs to

compensate for the external VDDL supply condition. It is

important to use this function when selecting power supply

requirements for VDDL1,2. A logic “0” (ground) will indicate

2.5V operation and a logic “1” will indicate 3.3V operation.

This pin has an internal pull-up to VDD. This pin is a latched

input.

PD#

This is an asynchronous active Low Input pin used to Power

Down the device into a Low Power state by not removing the

power supply. The internal Clocks are disabled and the VCO

and Crystal are stopped. Powered Down will also place all the

Outputs in a low state at the end of their current cycle. The

latency of Power Down will not be greater than 3ms. This pin

is a Full-time input with a pull-up to VDD.

CPU_STOP#

This is a active Low Input pin used to stop the CPUCLK

clocks in an active low state. All other clocks will continue to

run while this function is enabled. The CPUCLK’s will have a

turn OFF latency and a turn ON latency of 2 or 3 CPU clocks.

This pin is a Full-time input with a pull-up to VDD.

PCI_STOP#

This is a synchronous active Low Input pin used to stop the

PCICLK (0:5) clocks in a low state. It will not effect PCICLK_F

or any other outputs. There is only one full PCI clock output

for Turn OFF or Turn ON latency. This pin is a Full-time input

with a pull-up to VDD.

SSM (0:1)

These pins define the input condition for the Spread Spectrum

amount of modulation. See Spread Spectrum functionality

table. Note that spreading is only done on the CPU/SDRAM/

PCI clocks no modulation is done on the REF, IOAPIC or

PLL2 (24, 48MHz) outputs.

These latched input pins are defined at power-on for logic Hi

or logic Low condition by external pull-up or pull-down

resistors, or the internal pull-up resistor to VDD. See shared

pin operation of Input/output pins on next page.

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