DM74AS651WM View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
DM74AS651WM Datasheet PDF : 8 Pages
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DM74AS651 Switching Characteristics
Symbol
Parameter
Conditions
From
To
Min
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
VCC = 4.5V to 5.5V
R1 = R2 = 500Ω
CL = 50 pF
90
2
CBA or CAB
A or B
2
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
A or B
2
B or A
1
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
2
SBA or SAB A or B
tPHL
Propagation Delay Time
HIGH-to-LOW Level Output
(Note 4)
2
tPZH
Output Enable Time
2
to HIGH Level Output
tPZL
Output Enable Time
to LOW Level Output
3
Enable GBA A
tPHZ
Output Disable Time
2
from HIGH Level Output
tPLZ
Output Disable Time
2
from LOW Level Output
tPZH
Output Disable Time
3
to HIGH Level Output
tPZL
Output Disable Time
to LOW Level Output
tPHZ
Output Disable Time
from HIGH Level Output
3
Enable GAB B
2
tPLZ
Output Disable Time
2
from LOW Level Output
Note 4: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Max
8.5
Units
MHz
ns
9
ns
8
ns
7
ns
11
ns
9
ns
10
ns
16
ns
9
ns
9
ns
11
ns
16
ns
10
ns
11
ns
5
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