MT89L85AN View Datasheet(PDF) - Mitel Networks
Part Name
Description
Manufacturer
MT89L85AN Datasheet PDF : 20 Pages
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Advance Information
MT89L85
Pin Description
Pin #
44
48
PLCC SSOP
Name
Description
23
24 R/W Read/Write (Input). This input controls the direction of the data bus lines (D0-D7)
during a microprocessor access.
24
26
CS Chip Select (Input). Active low input enabling a microprocessor read or write of
control register or internal memories.
25-27
29-33
27-29 D7-D0 Data Bus 7 to 0 (Bidirectional). These pins provide microprocessor access to data in
31-35
the internal control register, connect memory high, connect memory low and data
memory.
34
35-39
41-43
1,25,37
38-42
44-46
VSS Ground Rail.
STo7- ST-BUS Outputs 7 to 0 (Three-state Outputs). Serial data output streams. These
STo0 streams are composed of 32 channels at data rates of 2.048 Mbit/s.
44
47 ODE Output Drive Enable (Input). This is an output enable for the STo0 to STo7 serial
outputs. If this input is low STo0-7 are high impedance. If this input is high each
channel may still be put into high impedance by software control.
1
48 CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256
bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the
Connect Memory high locations.
6,18, 6,19,30, NC No Connection.
28,40 43
Functional Description
With the integration of voice, video and data services
into the same network, there has been an increasing
demand for systems which ensure that data at N x 64
Kbit/s rates maintain frame sequence integrity while
being transported through time slot interchange
circuits. Existing requirements demand time slot
interchange devices performing switching with
constant throughput delay while guaranteeing
minimum delay for voice channels.
The MT89L85 device provides both functions and
allows existing systems based on the MT8985 to be
easily upgraded to maintain the data integrity while
multiple channel data are transported. The device is
designed to switch 64 kbit/s PCM or N x 64 kbit/s
data. The MT89L85 can provide both frame integrity
for data applications and minimum throughput
switching delay for voice applications on a per
channel basis.
By using Mitel Message mode capability, the
microprocessor can access input and output time
slots on a per channel basis to control devices such
as the MITEL MT8972, ISDN Transceivers and T1/
CEPT trunk interfaces through the ST-BUS interface.
Different digital backplanes can be accepted by the
MT89L85 device without user's intervention. The
MT89L85 device provides an internal circuit that
automatically identifies the polarity and format of
frame synchronization input signals compatible to
ST-BUS and GCI interfaces.
Device Operation
A functional block diagram of the MT89L85 device is
shown in Figure 1. The serial ST-BUS streams
operate continuously at 2.048 Mb/s and are arranged
in 125 µs wide frames each containing 32 8-bit
channels. Eight input (STi0-7) and eight output
(STo0-7) serial streams are provided in the MT89L85
device allowing a complete 256 x 256 channel non-
blocking switch matrix to be constructed. The serial
interface clock for the device is 4.096 MHz, as
required in ST-BUS and GCI specifications.
Data Memory
The received serial data is converted to parallel
format by the on-chip serial to parallel converters
and stored sequentially in a 256-position Data
Memory. The sequential addressing of the Data
Memory is generated by an internal counter that is
reset by the input 8 kHz frame pulse (F0i) marking
the frame boundaries of the incoming serial data
streams.
Depending on the type of information to be switched,
the MT89L85 device can be programmed to perform
3
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