M36W0R6040B0 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M36W0R6040B0
64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
STMicroelectronics
M36W0R6040B0 Datasheet PDF : 18 Pages
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M36W0R6040T0, M36W0R6040B0
SUMMARY DESCRIPTION
The M36W0R6040T0 and M36W0R6040B0 are
Multiple Memory Products which combine two
memory devices; a 64-Mbit, Multiple Bank Flash
memories, the M58WR064FT/B, and a 16-Mbit
Pseudo SRAM, the M69AR024B. Recommended
operating conditions do not allow more than one
memory to be active at the same time.
The memory is offered in a Stacked TFBGA88
(8x10mm, 8x10 ball array, 0.8mm pitch) package.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
The memory is supplied with all the bits erased
(set to ‘1’).
Figure 2. Logic Diagram
VDDQ
VDDF
VPPF
VDDP
22
A0-A21
EF
GF
WF
RPF
WPF
LF
KF
16
DQ0-DQ15
WAITF
M36W0R6040T
M36W0R6040B
E1P
GP
WP
E2P
UBP
LBP
Table 1. Signal Names
A0-A19
Common Address Inputs
DQ0-DQ15 Common Data Input/Output
VDDF
Flash Memory Power Supply
VDDQ
Common Flash and PSRAM Power
Supply for I/O Buffers
VPPF
Common Flash Optional Supply
Voltage for Fast Program & Erase
VSS
Ground
VDDP
PSRAM Power Supply
NC
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash Memory Control Functions
A21-A20
Address Inputs for the Flash memory
only
LF
Latch Enable input
EF
Chip Enable input
GF
Output Enable input
WF
Write Enable input
RPF
Reset input
WPF
Write Protect input
KF
Burst Clock
WAITF
Wait Data in Burst Mode
PSRAM control functions
E1P
Chip Enable input
GP
Output Enable input
WP
Write Enable input
E2P
Power-down input
UBP
Upper Byte Enable input
LBP
Lower Byte Enable input
VSS
AI08448
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